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ISP1583 Datasheet(PDF) 51 Page - NXP Semiconductors |
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ISP1583 Datasheet(HTML) 51 Page - NXP Semiconductors |
51 / 87 page Philips Semiconductors ISP1583 Hi-Speed USB peripheral controller Product data Rev. 03 — 12 July 2004 51 of 87 9397 750 13461 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. In 8-bit bus mode, the 16-bit Task File register 1F0 requires two consecutive write/read accesses before the proper PIO write/read is generated on the IDE interface. The first byte is always the lower byte (LSByte). Other Task File registers can be directly accessed. Writing to Task File registers can be done in any order except for the Task File register 1F7, which must be written last. Table 58: Task File register functions Task file ATA function ATAPI function 1F0 data (16-bits) data (16-bits) 1F1 error/feature error/feature 1F2 sector count interrupt reason 1F3 sector number/LBA[7:0] reserved 1F4 cylinder low/LBA[15:8] cylinder low 1F5 cylinder high/LBA[23:16] cylinder high 1F6 drive/head/LBA[27:24] drive select 1F7 command status/command 3F6 alternate status/command alternate status/command 3F7 drive address reserved Table 59: ATAPI peripheral register addressing Task file CS1_N CS0_N DA2 DA1 DA0 1F0 H LLLL 1F1 H LLLH 1F2 H L L H L 1F3 H L L H H 1F4 HL HL L 1F5 HL HL H 1F6 HL HHL 1F7 HL HHH 3F6 L HHHL 3F7 L HHHH Table 60: Task File 1F0 register (address: 40h): bit allocation CS1_N = H, CS0_N = L, DA2 = L, DA1 = L, DA0 = L. Bit 7 6 5 4 3 2 1 0 Symbol data (ATA or ATAPI) Reset 00000000 Bus reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W |
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