ISP1582 datasheet(35/66 Pages) PHILIPS

Part #	ISP1582

Description	Hi-Speed Universal Serial Bus peripheral controller

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

ISP1582

Hi-Speed USB peripheral controller

Preliminary data

Rev. 03 — 25 August 2004

35 of 66

9397 750 13699

Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is

programmed as 64 bytes, the Buffer Length register need not be ﬁlled. This is

because the transfer size is a multiple of MaxPacketSize, and the MaxPacketSize

packets will be automatically validated because the last packet is also of

MaxPacketSize.

Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is

programmed as 64 bytes, the Buffer Length register should be ﬁlled with 62 bytes just

before the MCU writes the last packet of 62 bytes. This ensures that the last packet,

which is a short packet of 62 bytes, is automatically validated.

Use bit VENDP in the Control register if you are not using the Buffer Length register.

This is applicable only to PIO mode access.

OUT endpoint: The DATACOUNT value is automatically initialized to the number of

data bytes sent by the host on each ACK.

Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized

packet is output as the lower byte (LSByte).

Remark: Buffer Length is valid only after an interrupt is generated for the bulk

endpoint.

9.3.5

Buffer Status register (address: 1Eh)

This register is accessed using index. The endpoint index must ﬁrst be set before

accessing this register for the corresponding endpoint. It reﬂects the status of the

double buffered endpoint FIFO. This register is valid only when the endpoint is

conﬁgured to be a double buffer.

Remark: This register is not applicable to the control endpoint.

Table 39 shows the bit allocation of the Buffer Status register.

Table 37:

Buffer Length register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

DATACOUNT[15:8]

Reset

00000000

Bus reset

00000000

Access

R/W

Bit

7

6

5

4

3

2

1

0

Symbol

DATACOUNT[7:0]

Reset

00000000

Bus reset

00000000

Access

R/W

Table 38:

Buffer Length register: bit description

Bit

Symbol

Description

15 to 0

DATACOUNT[15:0] Determines the current packet size of the indexed endpoint

FIFO.

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