Register Map

FUNCTION

ADDRESS

R/W BITS

DATA WIDTH

DATA

Read or Write Mode Register

0001

1 or 0

16

Mode Register

Read Conversion Result*

0010

1

20

Conversion Result

Read Chip ID

0100

1

8

Chip ID

Reserved, Do Not Use

All other

—

—

Reserved, Do Not Use

*Conversion result can also be read as shown in Figures 5, 6, and 7.

Mode Register

The reset state is: 0x0000. That is, the reference buffers are enabled if a valid reference voltage is applied at the REFIN

pin. If external reference buffers are used, tie REFIN low and the buffers will be automatically powered down.

DD[2:0] program the driver strength on DOUT pin. Higher driver strengths are for systems that have larger capacitive

loads on DOUT. The lowest driver strength that works should be chosen to save power and improve performance.

The driver strength is ordered from 1 to 6. The driver strength 1 is the weakest while the driver strength 6 is the strongest.

Table 5 shows the mapping between the register value D[2:0] and the correspondent driver strength.

Table 5. DOUT Driver Strength

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

Reset

—

—

—

—

—

DD2

DD1

DD0

—

—

PD

REF1

POR

pass

OTP

busy

OB

PD

REF2

Reset:

Reset the part when high.

DD[2:0]:

Program the driver strength on DOUT.

PD REF1:

Power down the first reference buffer when set.

POR pass:

High to indicate that POR was successful. If this bit is low, RESET should be asserted.

OTP busy:

High to indicate that the device is powering up.

OB:

Output data format is offset binary when high. two’s complement when low.

PD REF2:

Power down the second reference buffer when set.

DD[2:0]

DRIVER STRENGTH

000

4

001

5

010

6

011

Not Valid

100

1

101

2

110

3

111

Not Valid

MAX11905

20-Bit, 1.6Msps, Low-Power, Fully Differential

SAR ADC

www.maximintegrated.com

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