1

IN

2

GND

3

EN

4

FB/NR

5

OUT

3

TPS73601-Q1, TPS73625-Q1, TPS73633-Q1

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SLVSAI3A – SEPTEMBER 2010 – REVISED MAY 2016

Product Folder Links: TPS73601-Q1

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5 Pin Configuration and Functions

DBV Package

5-Pin S0T-23

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

EN

3

I

Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown

mode. See Enable Pin and Shutdown for more information. EN can be connected to IN if not used.

FB

4

I

FB pin for adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set

the output voltage of the device.

GND

2

G

Ground

IN

1

P

Input supply

NR

4

I

NR pin for fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated

by the internal bandgap, reducing output noise to very low levels.

OUT

5

P

Output of the regulator. There are no output capacitor requirements for stability.

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

see

(1)

MIN

MAX

UNIT

–0.3

6

V

–0.3

6

V

–0.3

5.5

V

–0.3

6

V

Peak output current

Internally limited

Output short-circuit duration

Indefinite

–40

150

°C

–40

125

°C

–65

150

°C

(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

±2000

V

Charged-device model (CDM), per AEC Q100-011

±500