TPS72301-Q1

TPS72325-Q1

SLVSAJ4B – SEPTEMBER 2010 – REVISED SEPTEMBER 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

(2)

TOP-SIDE MARKING

TPS72301QDBVRQ1

Adjustable output voltage

PPHQ

TPS72325QDBVRQ1

Nominal output voltage = 2.5 V

PSBQ

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2)

Output voltages from –1.2 V to –9 V in 100-mV increments are available. Minimum order quantities apply; contact factory for details and

availability.

ABSOLUTE MAXIMUM RATINGS

(1) (2)

Over operating temperature range, unless otherwise noted.

VALUE

UNITS

–11 to 0.3

V

–11 to 5.5

V

V

Internally limited

Output short-circuit duration

Indefinite

See Power Dissipation Ratings table

–55 to 150

°C

–65 to 150

°C

Latch-up performance meets 100 mA per AEC-Q100 | Class I

100

mA

Human-body model

2000

kV

ESD ratings

Machine model

200

V

Charged-device model

500

V

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to network ground terminal.

POWER DISSIPATION RATINGS

DERATING FACTOR

POWER

POWER

POWER

BOARD

PACKAGE

RATING

RATING

RATING

DBV

64°C / W

255°C / W

3.9 mW / °C

390 mW

215 mW

155 mW

DBV

64°C / W

180°C / W

5.6 mW / °C

560 mW

310 mW

225 mW

(1)

The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3- inch (7,62-cm × 7,62-cm), two-layer board with 2-ounce

(0.071-mm thick) copper traces on top of the board.

(2)

The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch (7,62-cm × 7,62-cm), multilayer board with 1-

ounce (0.035-mm thick) internal power and ground planes and 2-ounce (0.071-mm thick) copper traces on the top and bottom of the

board.

2

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