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TPS72118DBVT Datasheet(PDF) 2 Page - Texas Instruments |
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TPS72118DBVT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 16 page www.ti.com ABSOLUTE MAXIMUM RATINGS PACKAGE DISSIPATION RATING TPS72101 ,, TPS72115 TPS72116, TPS72118 SLVS352C – DECEMBER 2001 – REVISED MARCH 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TJ VOLTAGE PACKAGE PART NUMBER SYMBOL Adjustable TPS72101DBVT(1) TPS72101DBVR(2) PEKI 1.5 V TPS72115DBVT(1) TPS72115DBVR(2) PEII SOT-23 -40°C to 125°C (DBV) 1.6 V TPS72116DBVT(1) TPS72116DBVR(2) PHFI 1.8 V TPS72118DBVT(1) TPS72118DBVR(2) PEJI (1) The DBVT indicates tape and reel of 250 parts. (2) The DBVR indicates tape and reel of 3000 parts. over operating free-air temperature range unless otherwise noted(1)(2) TPS72101, TPS72115, TPS72116, TPS72118 Voltage range at IN -0.3 V to 7 V Voltage range at EN -0.3 V to 7 V Voltage on OUT, FB, NC -0.3 V to VI + 0.3 V Peak output current Internally limited ESD rating, HBM 3 kV Continuous total power dissipation See Dissipation Rating Table Operating junction temperature range, TJ -40°C to 150°C Storage temperature range, Tstg -65°C to 150°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.All voltage values are with respect to network ground terminal. (2) All voltage values are with respect to network ground terminal. DERATING FACTOR TA ≤ 25°C TA = 70°C TA = 85°C BOARD PACKAGE RΘJC RΘJA ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING Low-K(1) DBV 65.8 °C/W 259 °C/W 3.9 mW/°C 386 mW 212 mW 154 mW High-K(2) DBV 65.8 °C/W 180 °C/W 5.6 mW/°C 555 mW 305 mW 222 mW (1) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2 ounce copper traces on top of the board. (2) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. 2 Submit Documentation Feedback |
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