DS17485/DS17487

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During interval 5, the system is fully powered down. Battery backup of the clock calendar and NV RAM

RAM Clear

The DS17485/DS17487 provides a RAM clear function for the 114 bytes of user RAM. When enabled,

The RAM clear function is enabled or disabled through the RAM clear-enable bit (RCE; bank 1, register

04BH). When this bit is set to a logic 1, the 114 bytes of user RAM is cleared (all bits set to 1) when an

settings or upon the contents of the extended RAM. The RAM clear flag (RF, bank 1, register 04AH) is

4k x 8 Extended RAM

The DS17485/DS17487 provides 4k x 8 of on-chip SRAM that is controlled as nonvolatile storage

sustained from a lithium battery. On power-up, the RAM is taken out of write-protect status by the

internal power-OK signal (POK) generated from the write-protect circuitry. The on-chip 4k x 8 NV

SRAM is accessed through the eight multiplexed address/data lines AD7 to AD0. Access to the SRAM is

controlled by three on-chip latch registers. Two registers are used to hold the SRAM address, and the

other register is used to hold read/write data. The SRAM address space is from 00h to 0FFFh.

Access to the extended 4k x 8 RAM is controlled by three of the Dallas registers shown in Figure 4. The

Dallas registers in bank 1 must first be selected by setting the DV0 bit in register A to a logic 1. The 12-

bit address of the RAM location to be accessed must be loaded into the extended RAM address registers

located at 50h and 51h. The least significant address byte should be written to location 50h, and the most

significant 4-bits (right-justified) should be loaded in location 51h. Data in the addressed location can be

read by performing a read operation from location 53h, or written to by performing a write operation to

location 53h. Data in any addressed location can be read or written repeatedly without changing the

address in location 50h and 51h.

To read or write consecutive extended RAM locations, a burst mode feature can be enabled to increment

the extended RAM address. To enable the burst mode feature, set the BME bit in the extended control

register 4Ah, to a logic 1. With burst mode enabled, write the extended RAM starting address location to

registers 50h and 51h. Then read or write the extended RAM data from/to register 53h. The extended

register 53h is being accessed. Refer to the Burst Mode Timing Waveform.