DS1689/DS1693

9 of 32

The application software can select which interrupts, if any are to be used. There are a total of 6 bits

including 3 bits in Register B and 3 bits in Extended Register B which enable the interrupts. The extended

register locations are described later. Writing a logic 1 to an interrupt enable bit permits that interrupt to

will immediately be set at an active level, even though the event initiating the interrupt condition may

have occurred much earlier. As a result, there are cases where the software should clear these earlier

generated interrupts before first enabling new interrupts.

When an interrupt event occurs, the relating flag bit is set to a logic 1 in Register C or in Extended

Register A. These flag bits are set regardless of the setting of the corresponding enable bit located either

in Register B or in Extended Register B. The flag bits can be used in a polling mode without enabling the

corresponding enable bits.

However, care should be taken when using the flag bits of Register C as they are automatically cleared to

0 immediately after they are read. Double latching is implemented on these bits so that bits which are set

remain stable throughout the read cycle. All bits which were set are cleared when read and new interrupts

which are pending during the read cycle are held until after the cycle is completed. One, 2, or 3 bits can

be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no

interrupts are lost.

The flag bits in Extended Register A are not automatically cleared following a read. Instead, each flag bit

can be cleared to 0 only by writing 0 to that bit.

the six possible interrupt sources has it s flag and enable bits both set. The IRQF bit in Register C is a 1

determination that the DS1689/DS1693 initiated an interrupt is accomplished by reading Register C and

finding IRQF=1. IRQF will remain set until all enabled interrupt flag bits are cleared to 0.

SQUARE WAVE OUTPUT SELECTION

The SQW pin can be programmed to output a variety of frequencies divided down from the 32.768 kHz

crystal tied to X1 and X2. The square wave output is enabled and disabled via the SQWE bit in Register

B. If the square wave is enabled (SQWE=1), then the output frequency will be determined by the settings

of the E32K bit in Extended Register B and by the RS3-0 bits in Register A. If the E32K = 1, then a

32.768 kHz square wave will be output on the SQW pin regardless of the settings of RS3-0.

If E32K = 0, then the square wave output frequency is determined by the RS3-0 bits. These bits control a

1-of-15 decoder, which selects one of 13 taps that divide the 32.768 kHz frequency. The RS3-0 bits

establish the SQW output frequency as shown in Table 2. In addition, RS3-0 bits control the periodic

interrupt selection as described below.

If SQWE1, E32K=1, and the Auxiliary Battery Enable bit (ABE, bank 1; register 04BH) is enabled, and

above requirements are not met, no square wave output signal will be generated on the SQW pin in the