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DS1085 Datasheet(PDF) 8 Page - Dallas Semiconductor |
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DS1085 Datasheet(HTML) 8 Page - Dallas Semiconductor |
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8 / 21 page  DS1085 8 of 21 Table 7a. PRESCALER P0 DIVISOR M SETTINGS 0M1 0M0 PRESCALER P0 DIVISOR “M” 0 0 1* 01 2 10 4 11 8 *Factory Default Setting Table 7b. PRESCALER P1 DIVISOR M SETTINGS 1M1 1M0 PRESCALER P1 DIVISOR “M” 0 0 1* 01 2 10 4 11 8 *Factory Default Setting NOTE: When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case for situations when OUT0 is not used. Under these conditions all the circuitry associated with OUT0 is powered down. OUT0 is powered down (see Table 2). PDN1 (Default Setting = 0) If PDN1 = 1, CTRL1 functions as a power-down (see Table 3). If PDN1 = 0, CTRL1 functions as an output enable for OUT1 (see Table 3). NOTES FOR OUTPUT ENABLE AND POWER-DOWN: 1) Both enables are “smart” and wait for the output to be low before going to High-Z. 2) A power-down sequence first disables both outputs before powering down the device. 3) On power-up, the outputs are disabled until the clock has stabilized (~8000 cycles). 4) In power-down mode the device cannot be programmed. 5) A power-down command must persist for at least two cycles of the lowest output frequency plus 10µs. DIV WORD (N) (Address 01h) MSB LSB MSB LSB N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 XXXXXX First Data Byte Second Data Byte X = Don’t care. |
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