CY7C1382BV25-166BGC datasheet(6/30 Pages) CYPRESS

Part #	CY7C1382BV25-166BGC

Description	512K x 36 / 1 Mb x 18 Pipelined SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C1380BV25

CY7C1382BV25

PRELIMINARY

6

TMS

Test Mode Select

Synchronous

This pin controls the Test Access Port state machine. Sampled on the rising

edge of TCK (BGA Only).

TCK

JTAG serial

clock

Serial clock to the JTAG circuit (BGA Only).

VDD

Power Supply

Power supply inputs to the core of the device. Should be connected to 3.3V

–5% +10% power supply.

VSS

Ground

Ground for the core of the device. Should be connected to ground of the sys-

tem.

VDDQ

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V –5% +10%

power supply.

VSSQ

I/O Ground

Ground for the I/O circuitry. Should be connected to ground of the system.

NC

-

No Connects.

Pin Definitions

Name

I/O

Description

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CY7C1382BV25-166BGC Datasheet(PDF) 6 Page - Cypress Semiconductor

CY7C1382BV25-166BGC Datasheet(HTML) 6 Page - Cypress Semiconductor

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