CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 9 of 40
mented each time a new word is clocked to its output register.
The state machine that controls an Output Ready flag monitors
a Write pointer and Read pointer comparator that indicates
when the FIFO SRAM status is empty, empty + 1, or empty + 2.
In FWFT Mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and three
cycles have not elapsed since the time the word was written.
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
In the CY Standard mode, from the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data
available for reading in a minimum of two cycles of the Empty
Flag synchronizing clock. Therefore, an Empty Flag is LOW if
a word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty Flag HIGH; only then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchronization cycle of a
Write if the clock transition occurs at time tSKEW1 or greater
after the Write. Otherwise, the subsequent clock cycle will be
the first synchronization cycle.
Full/Input Ready Flags (FFA/IRA, FFC/IRC)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IRA and IRC) function is selected. In CY Standard mode, the
Full Flag (FFA and FFC) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
any Writes to the FIFO are ignored.
The Full/Input Ready flag of a FIFO is synchronized to the port
clock that writes data to its array. For both FWFT and CY
Standard modes, each time a word is written to a FIFO, its
Write pointer is incremented. The state machine that controls
a Full/Input Ready flag monitors a Write pointer and Read
pointer comparator that indicates when the FIFO SRAM status
is full, full – 1, or full – 2. From the time a word is read from a
FIFO, its previous memory location is ready to be written to in
a minimum of two cycles of the Full/Input Ready flag synchro-
nizing clock. Therefore, a Full/Input Ready flag is LOW if less
than two cycles of the Full/Input Ready flag synchronizing
clock have elapsed since the next memory Write location has
been read. The second LOW-to-HIGH transition on the
Full/Input Ready flag synchronizing clock after the Read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchro-
nizing clock begins the first synchronization cycle of a Read if
the clock transition occurs at time tSKEW1 or greater after the
Read. Otherwise, the subsequent clock cycle will be the first
synchronization cycle.
Almost Empty Flags (AEA, AEB)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a Write pointer and
Read pointer comparator that indicates when the FIFO SRAM
status is almost empty, almost empty + 1, or almost empty + 2.
The Almost Empty state is defined by the contents of register
X1 for AEB and register X2 for AEA. These registers are
loaded with preset values during a FIFO reset, programmed
from Port A, or programmed serially (see Almost Empty flag
and Almost Full flag offset programming, above). An Almost
Empty flag is LOW when its FIFO contains X or less words and
is HIGH when its FIFO contains (X + 2) or more words (see
note 61).
The Almost Empty flag is set HIGH by the first LOW-to-HIGH
transition of its synchronizing clock after two FIFO Writes that
fills memory to the (X + 2) level. A LOW-to-HIGH transition of
an Almost Empty flag synchronizing clock begins the first
synchronization cycle if it occurs at time tSKEW2 or greater after
the Write that fills the FIFO to (X + 2) words. Otherwise, the
subsequent synchronizing clock cycle will be the first synchro-
nization cycle.
Almost Full Flags (AFA, AFC)
The Almost Full flag of a FIFO is synchronized to the port clock
that writes data to its array. The state machine that controls an
Almost Full flag monitors a Write pointer and Read pointer
comparator that indicates when the FIFO SRAM status is
almost full, almost full – 1, or almost full – 2. The Almost Full
state is defined by the contents of register Y1 for AFA and
register Y2 for AFC. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmed serially (see Almost Empty flag and Almost Full
flag offset programming above). An Almost Full flag is LOW
when the number of words in its FIFO is greater than or equal
to (1024 – Y) (4096 – Y) or (16384 – Y) for the CY7C436X6AV
respectively. An Almost Full flag is HIGH when the number of
words in its FIFO is less than or equal to [1024 – (Y + 2)] [4096
– (Y + 2)], or [16384 – (Y + 2)],for the CY7C436X6AV respec-
tively (see note 61).
The Almost Full flag is set HIGH by the first LOW-to-HIGH
transition of its synchronizing clock after two FIFO reads that
reduces the number of words in memory to [1024/4096/16384
– (Y + 2)]. A LOW-to-HIGH transition of an Almost Full flag
synchronizing clock begins the first synchronization cycle if it
occurs at time tSKEW2 or greater after the Read that reduces
the number of words in memory to [1024/4096/16384 –
(Y + 2)]. Otherwise, the subsequent synchronizing clock cycle
will be the first synchronization cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B/Port C without
putting it in queue. The Mailbox Select (MBA, MBB, MBC)
inputs choose between a mail register and a FIFO for a port
data transfer operation. The usable width of both the Mail1 and
Mail2 registers matches the selected bus size of Port B and C.
A LOW-to-HIGH transition on CLKA writes A0-35 data to the
Mail1 Register when a Port A Write is selected by CSA, W/RA,
and ENA with MBA HIGH.
When sending data from Port C to Port A via the Mail2
Register, the following is the case: A LOW-to-HIGH transition
on CLKC writes C0-17 data to the Mail2 Register when a Port
C Write is selected by WENC with MBC HIGH. If the selected
Port C bus size is 18 bits, then the usable width of the Mail2
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