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ISO5852S-Q1 Datasheet(PDF) 3 Page - Texas Instruments |
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ISO5852S-Q1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 42 page 1 VEE2 16 GND1 2 DESAT 15 VCC1 3 GND2 14 RST 4 OUTH 13 FLT 5 VCC2 12 RDY 6 OUTL 11 IN± 7 CLAMP 10 IN+ 8 VEE2 9 GND1 Not to scale 3 ISO5852S-Q1 www.ti.com SLLSEQ2 – SEPTEMBER 2016 Product Folder Links: ISO5852S-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 5 Description (continued) An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 μs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, VEE2, the gate-driver output is pulled hard to the VEE2 potential, turning the IGBT immediately off. When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input. When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions. The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high. The ISO5852S-Q1 device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient. 6 Pin Configuration and Function DW Package 16-Pin SOIC Top View Pin Functions PIN I/O DESCRIPTION NAME NO. CLAMP 7 O Miller clamp output DESAT 2 I Desaturation voltage input FLT 13 O Fault output, active-low during DESAT condition GND1 9 — Input ground 16 GND2 3 — Gate drive common. Connect to IGBT emitter. IN+ 10 I Non-inverting gate drive voltage control input IN– 11 I Inverting gate drive voltage control input OUTH 4 O Positive gate drive voltage output OUTL 6 O Negative gate drive voltage output RDY 12 O Power-good output, active high when both supplies are good. RST 14 I Reset input, apply a low pulse to reset fault latch. VCC1 15 — Positive input supply (2.25-V to 5.5-V) VCC2 5 — Most positive output supply potential. VEE2 1 — Output negative supply. Connect to GND2 for unipolar supply application. 8 |
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