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ISO721-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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ISO721-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 27 page ISO721-Q1, ISO722-Q1 www.ti.com SLLS918C – JULY 2008 – REVISED JUNE 2013 ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Quiescent 0.3 0.5 ICC1 VCC1 supply current VI = VCC or 0 V, No load mA 25 Mbps 1 2 ISO722-Q1 EN at VCC 200 μA Sleep Mode VI = VCC or 0 V, No load ICC2 VCC2 supply current EN at 0 V or ISO721- Quiescent 8 12 Q1 mA 25 Mbps VI = VCC or 0 V, No load 10 14 IOH = –4 mA, See Figure 1 VCC – 0.8 4.6 VOH High-level output voltage V IOH = –20 μA, See Figure 1 VCC – 0.1 5 IOL = 4 mA, See Figure 1 0.2 0.4 VOL Low-level output voltage V IOL = 20 μA, See Figure 1 0 0.1 VI(HYS) Input voltage hysteresis 150 mV IIH High-level input current IN at 2 V 10 μA IIL Low-level input current IN at 0.8 V –10 μA High-impedance output IOZ ISO722-Q1 EN, IN at VCC 1 μA current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) 1 pF CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 5 15 40 kV/ μs (1) For 5-V operation, VCC1 or VCC2 specification is from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 specification is from 3 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay, low-to-high-level output See Figure 1 17 30 ns tPHL Propagation delay , high-to-low-level output See Figure 1 17 30 ns tsk(p) Pulse skew |tPHL – tPLH| See Figure 1 0.5 3 ns tsk(pp) Part-to-part skew 0 5 ns (1) tr Output signal rise time See Figure 1 2 ns tf Output signal fall time See Figure 1 2 ns Sleep-mode propagation delay, tpHZ 7 9 15 ns high-level-to-high-impedance output See Figure 2 Sleep-mode propagation delay, tpZH 4.5 5 8 μs high-impedance-to-high-level output ISO722-Q1 Sleep-mode propagation delay, tpLZ 7 9 15 ns low-level-to-high-impedance output See Figure 3 Sleep-mode propagation delay, tpZL 4.5 5 8 μs high-impedance-to-low-level output tfs Failsafe output delay time from input power loss See Figure 4 3 μs 100-Mbps NRZ data input, 2 See Figure 6 tjit(PP) Peak-to-peak eye-pattern jitter ns 100-Mbps unrestricted bit run length data input, See 3 Figure 6 (1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ISO721-Q1 ISO722-Q1 |
Similar Part No. - ISO721-Q1_16 |
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Similar Description - ISO721-Q1_16 |
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