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BQ76PL455A Datasheet(PDF) 5 Page - Texas Instruments

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Part # BQ76PL455A
Description  16-Cell Industrial Integrated Battery Monitor
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

BQ76PL455A Datasheet(HTML) 5 Page - Texas Instruments

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bq76PL455A
www.ti.com
SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016
Product Folder Links: bq76PL455A
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Copyright © 2016, Texas Instruments Incorporated
Pin Functions (continued)
NAME
TYPE(1)
DESCRIPTION
PIN
NO.
FAULTH+
57
DI
Non-inverting, high-side differential connection to the FAULTL+ pin of the higher adjacent module in
a daisy chain.
Leave this pin unconnected if not used.
FAULTL–
51
DO
Inverting, low-side differential connection to the FAULTH– pin of the lower adjacent module in a
daisy chain.
Leave this pin unconnected if not used.
FAULTL+
50
DO
Non-inverting, low-side differential connection to the FAULTH+ pin of the lower adjacent module in a
daisy chain.
Leave this pin unconnected if not used.
GPIO0
47
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
GPIO1
46
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
GPIO2
45
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
GPIO3
44
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
GPIO4
43
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
GPIO5
42
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input.
Do not allow GPIO pins to float when configured as inputs.
NC1
36
NC
Do not connect to this pin. This pin must remain floating for correct operation.
NC2
75
NC
Do not connect to this pin. This pin must remain floating for correct operation.
NPNB
71
AO
Internal voltage regulator controller output pin. Connect to the base of the external NPN transistor.
Leave unconnected if not used.
OUT1
73
AO
Analog multiplexer output. Connect a 390-pF filter capacitor type C0G or NP0 between this pin and
AGND. Connect externally to pin OUT2. Internally tied to pin OUT2.
OUT2
68
AI
ADC input pin. Connect externally to pin OUT1. Internally tied to pin OUT1.
RX
39
DI
Single-ended UART receive input. This pin must be either:
Driven from a UART signal OR
Pulled up to VIO
Do not allow this pin to float at any time.
TOP
76
P
Power supply input and module voltage-measurement pin. Connect to the top cell of the module
through a series resistor. Requires a decoupling capacitor(3) from TOP to the ground plane. See
TOP Pin Connection for details. Locate decoupling capacitor as close to pin as possible. The low-
pass filter created by the RC should have a tau similar to the low-pass filter used in the VSENSE
circuits. See VP Regulated Output or Application and Implementation for component selection
details.
TX
38
DO
Single-ended UART transmit output. Leave this pin unconnected if not used.
V5VAO
58
P
Connection to internal 5-V always-on supply. Decouple with a 4.7-µF capacitor(3) connected to the
ground plane. Locate decoupling capacitor as close to pin as possible. This pin should not be used
to supply external circuitry.
VDIG
34
P
5.3-V Digital Supply input. Always connect VDIG to VP with 1-Ω resistor. Decouple with 4.7-µF and
0.1-µF capacitors(3) in parallel to the ground plane. Locate decoupling capacitors as close to the
VDIG pin as possible.
VIO
41
P
3-V to 5-V power input for IO supply. Connect this pin to the same power supply used to drive the
source/receiver for the GPIO, FAULT_N, RX, and TX pins. Typically, connect this pin to VP/VDIG
for all devices except the base device in the stack. In the base (or single) device, this pin is typically
driven from the same supply as the microcontroller I/O pins.
If VP/VDIG is connected as the power source, this pin should be decoupled with a 0.1-µF
capacitor(3) to the digital ground plane. Place a 1-Ω resistor in series from VP to VIO. Locate the
decoupling capacitor as close to the VIO pin as possible.
If another supply is used, decouple with parallel 10-µF and 0.1-µF capacitors(3).
VM
31
P
Internal –5-V charge pump output. Decouple with 4.7-µF and 0.1-µF capacitors(3) in parallel to the
ground plane. Locate decoupling capacitor as close to pin as possible.


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