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TPS65070TRSLRQ1 Datasheet(PDF) 40 Page - Texas Instruments |
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TPS65070TRSLRQ1 Datasheet(HTML) 40 Page - Texas Instruments |
40 / 91 page TSX1 TSX2 TSY1 TSY2 RX1 RX2 R Y1 R Y2 R C NMOS NMOS TSREF TGATE TOINT BLOCK STANDBY MODE TGATE 22kW TRESHOLD DETECTOR Dataline stable; datavalid DATA CLK Change ofdata allowed TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 SLVSAP7 – JANUARY 2011 www.ti.com Figure 38. Touch Screen Standby Mode I2C Interface Specification: Serial interface The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. The has a 7-Bit address: ‘1001000’, other addresses are available upon contact with the factory. Attempting to read data from register addresses not listed in this section will result in 00h being read out. For normal data transfer, SDAT is allowed to change only when SCLK is low. Changes when SCLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per Bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the device generates an acknowledge Bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge Bit. The device must pull down the SDAT line during the acknowledge clock pulse so that the SDAT line is a stable low during the high period of the acknowledge clock pulse. The SDAT line is a stable low during the high period of the acknowledge–related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge Bit on the last byte that was clocked out of the slave. In this case, the slave device must leave the data line high to enable the master to generate the stop condition. All registers are set to their default value by one of these conditions: • Voltage is below the UVLO threshold defined with registers <UVLO1>, <UVLO0> • PB_IN is asserted LOW for >15s (option) Figure 39. Bit Transfer on the Serial Interface 40 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 |
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