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HFCT-5962TL Datasheet(PDF) 8 Page - Agilent(Hewlett-Packard) |
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HFCT-5962TL Datasheet(HTML) 8 Page - Agilent(Hewlett-Packard) |
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8 / 17 page  7 Application Information The Applications Engineering Group at Agilent is available to assist you with technical understanding and design trade- offs associated with these transceivers. You can contact them through your Agilent sales representative. The following information is provided to answer some of the most common questions about the use of the parts. Optical Power Budget and Link Penalties The worst-case Optical Power Budget (OPB) in dB for a fiber- optic link is determined by the difference between the Figure 6a. Recommended dc coupled interface circuit minimum transmitter output optical power (dBm avg) and the lowest receiver sensitivity (dBm avg). This OPB provides the necessary optical signal range to establish a working fiber-optic link. The OPB is allocated for the fiber-optic cable length and the corresponding link penalties. For proper link performance, all penalties that affect the link performance must be accounted for within the link optical power budget. Electrical and Mechanical Interface Recommended Circuit Figures 6a and 6b show recommended dc and ac coupled circuits for deploying the Agilent transceivers in +3.3 V systems. Data Line Interconnections Agilent’s HFCT-5964TL/TG/NL/ NG/ATL/ATG fiber-optic transceivers are designed to couple to +3.3 V PECL signals. The transmitter driver circuit regulates the output optical power. The regulated light output will maintain a constant output optical power provided the data pattern is reasonably balanced in duty cycle. If the data duty cycle has long, continuous state times (low or high data duty cycle), then the output optical power will gradually change its average output optical power level to its preset value. Z = 50 W Z = 50 W Z = 50 W Z = 50 W SD LVTTL LVPECL V CC (+3.3 V) V CC (+3.3 V) RD+ RD- Z = 50 W 1 T X R X 130 W 130 W 130 W 130 W V CC RX (+3.3 V) P MON+ P MON- B MON+ B MON- T DIS (LVTTL) 23 45 67 8 9 10 20 19 18 17 16 15 14 13 12 11 TD- TD+ Note: C1 = C2 = C3 = 10 nF or 100 nF Note A: THE BIAS RESISTOR FOR VpdR SHOULD NOT EXCEED 200 W * C4 AND C5 ARE OPTIONAL BYPASS CAPACITORS FOR ADDITIONAL LOW FREQUENCY NOISE FILTERING. 200 W NOTE A 10 nF 1 µH C2 1 µH C1 C3 10 µF V CC (+3.3 V) C4 * 10 µF C5 * 10 µF 100 W 100 W TERMINATE AT TRANSCEIVER INPUTS PHY DEVICE LVPECL TERMINATE AT DEVICE INPUTS |
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