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ADV7181 Datasheet(PDF) 68 Page - Analog Devices |
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ADV7181 Datasheet(HTML) 68 Page - Analog Devices |
68 / 96 page ADV7181B Rev. 0 | Page 68 of 96 Bit Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0 Closed captioning not detected in the input video signal CCAPD_Q 1 Closed captioning data detected in the video input signal 0 Gemstar data not detected in the input video signal GEMD_Q 1 Gemstar data detected in the input video signal 0 No change detected in CGMS data in the input video signal CGMS_CHNGD_Q 1 A change is detected in the CGMS data in the input video signal 0 No change detected in WSS data in the input video signal WSS_CHNGD_Q 1 A change is detected in the WSS data in the input video signal Reserved x Not used Reserved x Not used Reserved x Not used 0 Manual interrupt not set 0x46 Interrupt Status 2 Read-Only Register Register Access Page 2 MPU_STIM_INTRQ_Q 1 Manual interrupt set These bits can be cleared or masked by Registers 0x47 and 0x48, respectively. 0 Do not clear CCAPD_CLR 1 Clears CCAPD_Q bit 0 Do not clear GEMD_CLR 1 Clears GEMD_Q bit 0 Do not clear CGMS_CHNGD_CLR 1 Clears CGMS_CHNGD_Q bit 0 Do not clear WSS_CHNGD_CLR 1 Clears WSS_CHNGD_Q bit Reserved x Not used Reserved x Not used Reserved x Not used 0 Do not clear 0x47 Interrupt Clear 2 Write-Only Register Access Page 2 MPU_STIM_INTRQ_CLR 1 Clears MPU_STIM_INTRQ_Q bit 0 Do not mask CCAPD_MSKB 1 Masks CCAPD_Q bit 0 Do not mask GEMD_MSKB 1 Masks GEMD_Q bit 0 Do not mask CGMS_CHNGD_MSKB 1 Masks CGMS_CHNGD_Q bit 0 Do not mask WSS_CHNGD_MSKB 1 Masks WSS_CHNGD_Q bit Reserved 0 Not used Reserved 0 Not used Reserved 0 Not used 0 Do not mask 0x48 Interrupt Mask 2 Read / Write Register Access Page 2 MPU_STIM_INTRQ_MSKB Masks MPU_STIM_INTRQ_Q bit |
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