AD9235BCP-65 datasheet(2/32 Pages) AD

Part #	AD9235BCP-65

Description	12-Bit, 20/40/65 MSPS 3 V A/D Converter

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REV. B

–2–

AD9235–SPECIFICATIONS

DC SPECIFICATIONS

Test

AD9235BRU-20

AD9235BRU-40

AD9235BRU/BCP-65

Parameter

Temp

Level

Min Typ

Max

Min Typ

Max

Min Typ

Max

Unit

RESOLUTION

Full

VI

12

Bits

ACCURACY

No Missing Codes Guaranteed

Full

VI

12

Bits

Offset Error

Full

VI

±0.30 ±1.20

±0.50 ±1.20

% FSR

Gain Error

1

Full

VI

±0.30 ±2.40

±0.50 ±2.50

±0.50 ±2.60

% FSR

Differential Nonlinearity (DNL)

2

Full

IV

±0.35 ±0.65

±0.35 ±0.75

±0.40 ±0.80

LSB

25

°CI

±0.35

LSB

Integral Nonlinearity (INL)

2

Full

IV

±0.45 ±0.80

±0.50 ±0.90

±0.70 ±1.30

LSB

25

°CI

±0.40

±0.45

LSB

TEMPERATURE DRIFT

Offset Error

Full

V

±2

±3

ppm/

°C

Gain Error

1

Full

V

±12

ppm/

°C

INTERNAL VOLTAGE

REFERENCE

Output Voltage Error (1 V Mode)

Full

VI

±5

±35

±5

±35

±5

±35

mV

Load Regulation @ 1.0 mA

Full

V

0.8

mV

Output Voltage Error (0.5 V Mode)

Full

V

±2.5

mV

Load Regulation @ 0.5 mA

Full

V

0.1

mV

INPUT REFERRED NOISE

VREF = 0.5 V

25

°CV

0.54

LSB rms

VREF = 1.0 V

25

°CV

0.27

LSB rms

ANALOG INPUT

Input Span, VREF = 0.5 V

Full

IV

1

V p-p

Input Span, VREF = 1.0 V

Full

IV

2

V p-p

Input Capacitance

3

Full

V

7

pF

REFERENCE INPUT

RESISTANCE

Full

V

7

k

Ω

POWER SUPPLIES

Supply Voltages

AVDD

Full

IV

2.7

3.0

3.6

2.7

3.0

3.6

2.7

3.0

3.6

V

DRVDD

Full

IV

2.25 3.0

3.6

2.25 3.0

3.6

2.25 3.0

3.6

V

Supply Current

IAVDD

2

Full

V

30

55

100

mA

IDRVDD

2

Full

V

2

5

7

mA

PSRR

Full

V

±0.01

% FSR

POWER CONSUMPTION

DC Input

4

Full

V

90

165

300

mW

Sine Wave Input

2

Full

VI

95

110

180

205

320

350

mW

Standby Power

5

Full

V

1.0

mW

NOTES

1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).

2Measured at maximum clock rate, f

IN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.

3Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2 for the equivalent analog input structure.

4Measured with dc input at maximum clock rate.

5Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).

Specifications subject to change without notice.

(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, 2 V p-p Differential Input,

1.0 V internal reference, TMIN to TMAX, unless otherwise noted.)

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AD9235BCP-65 Datasheet(PDF) 2 Page - Analog Devices

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