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74AUP1G58 Datasheet(PDF) 3 Page - Diodes Incorporated |
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74AUP1G58 Datasheet(HTML) 3 Page - Diodes Incorporated |
3 / 16 page 74AUP1G58 Document number: DS36853 Rev. 1 - 2 3 of 16 www.diodes.com June 2015 © Diodes Incorporated 74AUP1G58 Logic Configurations B C Y B C Y 2-Input NAND Gate 2-Input OR Gate with Both Inputs Inverted Configuration 1 C Y B 4 3 2 5 6 1 Vcc 2-Input AND Gate with B Input Inverted 2-Input NOR Gate with C input Inverted Configuration 2 C Y B 4 3 2 5 6 1 Vcc B C Y B C Y 2-Input AND Gate with C Input Inverted 2-Input NOR Gate with A Input Inverted Configuration 3 C Y A 4 3 2 5 6 1 Vcc Y A C A C Y 2-Input OR Gate 2-Input NAND Gate with Both Inputs Inverted Configuration 4 C Y A 4 3 2 5 6 1 Vcc Y A C A C Y 2-Input XOR Gate Configuration 5 B C C Y B 4 3 2 5 6 1 Vcc Y Buffer Configuration 6 Y A 4 3 2 5 6 1 Vcc Y A Function Selection Table Logic Function Configuration 2-Input NAND 1 2-Input NAND with both inputs inverted 4 2-Input AND with inverted input 2,3 2-Input NOR with inverted input 2,3 2-Input OR 4 2-Input OR with both inputs inverted 1 2-Input XOR 5 1-Input Buffer 6 |
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