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DA14582 Datasheet(PDF) 71 Page - Dialog Semiconductor |
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DA14582 Datasheet(HTML) 71 Page - Dialog Semiconductor |
71 / 177 page © 2015 Dialog Semiconductor 70 Preliminary - March 11, 2015 v2.0 4 R UART_CTS Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the UART Ctrl. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS). 0x0 3 R UART_DDCD Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. 0x0 2 R UART_TERI Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. 0x0 1 - - Reserved 0x0 0 R UART_DCTS Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on cts_n since last read of MSR 1 = change on cts_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. 0x0 Table 102: UART_MSR_REG (0x50001018) Bit Mode Symbol Description Reset Table 103: UART_SCR_REG (0x5000101C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W UART_SCRATCH_PA D This register is for programmers to use as a temporary stor- age space. It has no defined purpose in the UART Ctrl. 0x0 Table 104: UART_LPDLL_REG (0x50001020) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 |
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