Electronic Components Datasheet Search |
|
DA9053-XXHA1-A Datasheet(PDF) 6 Page - Dialog Semiconductor |
|
DA9053-XXHA1-A Datasheet(HTML) 6 Page - Dialog Semiconductor |
6 / 183 page DA9053 Flexible High-Power System PMIC with 1.8 A Switching USB Power Manager Datasheet Revision 2.1 31-Aug-2016 CFR0011-120-00 6 of 183 © 2016 Dialog Semiconductor 30 Ordering Information ................................................................................................................ 181 30.1 Variants Ordering Information ........................................................................................... 181 Revision History .............................................................................................................................. 182 Figures Figure 1: Block Diagram ...................................................................................................................... 10 Figure 2: DA9053 Ballout (View From Top, Balls Through Package) ................................................. 13 Figure 3: 2-Wire Control Bus Timing Diagram .................................................................................... 22 Figure 4: 4-Wire Control Bus Timing Diagram .................................................................................... 23 Figure 5: ID Detection Circuitry ........................................................................................................... 50 Figure 6: Schematic of the RTC Oscillator and Counter Functionality................................................ 52 Figure 7: BUCKPERI Efficiency Curves .............................................................................................. 54 Figure 8: BUCKCORE Efficiency Curves ............................................................................................ 54 Figure 9: BUCKPRO Efficiency Curves............................................................................................... 54 Figure 10: BUCKMEM Efficiency Curves ............................................................................................ 54 Figure 11: BUCKPRO Load Regulation Transient .............................................................................. 54 Figure 12: BUCKPRO Line Regulation Transient ............................................................................... 54 Figure 13: Typical LDO Load Regulation ............................................................................................ 55 Figure 14: Typical LDO Drop-Out Voltage .......................................................................................... 55 Figure 15: Typical LDO Line Transient................................................................................................ 55 Figure 16: LDO Load Transient ........................................................................................................... 55 Figure 17: Typical LDO Voltage vs Temperature ................................................................................ 56 Figure 18: ADC DNL Performance ...................................................................................................... 56 Figure 19: ADC INL Performance ....................................................................................................... 56 Figure 20: Power Path Behaviour USB 100 Mode .............................................................................. 57 Figure 21: Power Path Behaviour USB 500 Mode .............................................................................. 57 Figure 22: Transitioning Supply from VCHG (via DCIN) to VBAT....................................................... 57 Figure 23: Transitioning Supply from USB 5 V (via VBUS) to VBAT .................................................. 57 Figure 24: WLED Current Performance .............................................................................................. 58 Figure 25: WLED Relative Accuracy ................................................................................................... 58 Figure 26: Boost Converter Efficiency Curves .................................................................................... 58 Figure 27: Boost Regulation Voltages ................................................................................................. 58 Figure 28: Control Ports and Interface ................................................................................................ 59 Figure 29: Schematic of a 4-Wire and 2-Wire Power Manager Bus ................................................... 62 Figure 30: 4- Wire Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’’)............... 63 Figure 31: 4- Wire Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘1’’)............... 63 Figure 32: 4- Wire Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’’)............... 64 Figure 33: 4-Wire Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’’)............... 64 Figure 34: Timing of 2-Wire START and STOP Condition .................................................................. 65 Figure 35: 2-Wire Byte Write (SO/DATA Line) .................................................................................... 66 Figure 36: Examples of 2-Wire Byte Read (SO/DATA line) ................................................................ 66 Figure 37: Examples of 2-Wire Page Read (SO/DATA line) ............................................................... 66 Figure 38: 2-Wire Page Write (SO/DATA line) .................................................................................... 67 Figure 39: 2-Wire Repeated Write (SO/DATA line)............................................................................. 67 Figure 40: Start-Up from NO-POWER to POWER-DOWN Mode ....................................................... 72 Figure 41: Content of OTP Power Sequencer Register Cell............................................................... 74 Figure 42: Allocation of Supplies (IDs) to the Sequencer Time Slots ................................................. 76 Figure 43: Typical Power-Up Timing ................................................................................................... 98 Figure 44: Power Mode Transitions .................................................................................................... 99 Figure 45: Smart Mirror TM Voltage Regulator .................................................................................... 104 Figure 46: DCDC Buck Converter ..................................................................................................... 106 Figure 47: BUCKPERI / BUCKMEM Output Switches ...................................................................... 107 Figure 48: DCCC and Active Diode Operation.................................................................................. 130 |
Similar Part No. - DA9053-XXHA1-A |
|
Similar Description - DA9053-XXHA1-A |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |