NCV7240BDPR2G datasheet(7/27 Pages) ONSEMI

Part #	NCV7240BDPR2G

Description	Octal Low-Side Relay Driver

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Manufacturer	ONSEMI [ON Semiconductor]

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NCV7240, NCV7240A, NCV7240B

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7

ELECTRICAL CHARACTERISTICS (3.0 V < VDD < VDDA, 4.5 V < VDDA (Note 7) < 5.5 V, −40

°C v TJ v 150°C, EN = VDD,

LHI = 0 V unless otherwise specified).

Characteristic

Unit

Max

Typ

Min

Conditions

OUTPUT TIMING SPECIFICATIONS

Serial Control

Output turn−on time

All Channels

CSB going high 80% to OUTx going low

20% Vbat ,Vbat = 13.5 V,

IDS = 180 mA resistive load

−

30

50

ms

Serial Control

Output turn−off time

All Channels

CSB going high 80% to OUTx going high

80% Vbat, Vbat = 13.5 V,

IDS = 180 mA resistive load

−

30

50

ms

Parallel Control

Output turn−on time

All Channels

INx going high 80% to OUTx going low

20% Vbat, Vbat = 13.5 V,

IDS = 180 mA resistive load

−

30

50

ms

Parallel Control

Output turn−off time

All Channels

Inx going low 20% to OUTx going high

80% Vbat, Vbat = 13.5 V,

IDS = 180 mA resistive load

−

30

50

ms

Over Load Shut−Down Delay Time

3

15

50

ms

Open Load Detection Time

30

115

200

ms

DIGITAL INTERFACE CHARACTERISTICS

INPUT CHARACTERISTICS

Digital Input Threshold

(CSB, SI, SCLK, LHI, EN,INx)

0.8

1.4

2.0

V

Digital Input Hysteresis

(CSB, SI, SCLK, INx)

50

175

300

mV

Digital Input Hysteresis

(LHI, EN)

150

400

800

mV

Input Pulldown Resistance

(SI, SCLK, LHI, EN,INx)

Inx = SI = SCLK = LHI = EN = VDD

50

120

190

k

W

Input Pullup Resistance (CSB)

CSB = 0 V

50

120

190

k

W

CSB Leakage to VDD

CSB = 5 V, VDD = 0 V

−

100

uA

CSB Leakage to VDDA

CSB = 5 V, VDDA = 0 V

−

100

uA

OUTPUT CHARACTERISTICS

SO – Output High

I(out) = −1.5 mA

VDD −

0.4

−

V

SO – Output Low

I(out) = 2.0 mA

−

0.6

V

SO Tri−state Leakage

CSB = VDD

−3

0

3

mA

SPI TIMING (all timing specifications measured at 20% and 80% voltage levels)

SCLK Frequency

−

5

MHz

SCLK Clock Period

200

−

ns

SCLK High Time

Figure 5, #1

85

−

ns

SCLK Low Time

Figure 5, #2

85

−

ns

SI Setup Time

Figure 5, #11

50

−

ns

SI Hold Time

Figure 5, #12

50

−

ns

CSB Setup Time

Figure 5, #5, 6

100

−

ns

CSB High Time

Figure 5, #7

1.5

−

ms

SCLK Setup Time

Figure 5, #3, 4

85

−

ns

SO Output Enable Time

(CSB falling to SO valid)

Figure 5, #8, Cload = 50 pF

Not ATE tested

−

200

ns

SO Output Disable Time

(CSB rising to SO tri−state)

Figure 5, #9

Not ATE tested

−

200

ns

SO Output Data Valid Time with capacitive load

Figure 5, #10, Cload = 50 pF

Not ATE tested

−

100

ns

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