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PESD1USB3SZ Datasheet(PDF) 3 Page - NXP Semiconductors |
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PESD1USB3SZ Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 19 page PESDXUSB3S_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 3 — 26 April 2016 3 of 19 NXP Semiconductors PESDxUSB3S series ESD protection for differential data lines 3. Ordering information 4. Marking 5. Limiting values Table 3. Ordering information Type number Package Name Description PESD1USB3S WLCSP5 wafer level chip-size package; 5 bumps (2-1-2) PESD2USB3S WLCSP10 wafer level chip-size package; 10 bumps (4-2-4) PESD3USB3S WLCSP15 wafer level chip-size package; 15 bumps (6-3-6) Table 4. Marking codes Type number Marking code PESD1USB3S PD1S PESD2USB3S PD2S PESD3USB3S PD3S Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VI input voltage -0.5 5 V VESD electrostatic discharge voltage IEC 61000-4-2, level 4; all input pins to ground contact discharge -15 15 kV air discharge -15 15 kV IEC 61000-4-2, level 4; all output pins to ground contact discharge -2 2 kV air discharge -2 2 kV IPPM rated peak-pulse current tp =8/20 s-8 8 A Tstg storage temperature -40 +125 °C Tamb ambient temperature -40 +85 °C |
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