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TLV320AIC12 Datasheet(PDF) 26 Page - Texas Instruments |
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TLV320AIC12 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 50 page  3–13 SCLK FS DIN DOUT 16-Bit DAC Data (Sample 1) 16-Bit ADC Data (Sample 1) Slot Number 0 Slot Number 0 16-Bit DAC Data (Sample 2) 16-Bit ADC Data (Sample 2) (Sample 3) (Sample 3) Data Frame Data Frame Figure 3–15. Standard Operation/Continuous Data Transfer Mode: Stand-Alone Timing SCLK FS DIN/ DOUT 0 12 n–1 n–2 n–3 01 2 n–1 n–2 n–3 Master Slave n–2 Slave n–3 Slave 2 Slave 1 Slave 0 Master Slave n–2 Slave n–3 Slave 2 Slave 1 Slave 0 Data Frame / Sample 1 NOTE: n is the total number of AIC14s in the cascade 16 SCLKs Per Time Slot Data Frame / Sample 2 Slot Number Figure 3–16. Standard Operation/Continuous Data Transfer Mode: Master-Slave Cascade Timing 3.8.3 Turbo Mode (SCLK) Setting TURBO = 1 (bit D7) in control register 2 enables the turbo mode that requires the following condition to be met: • For master with SCLK as output, M × N > #Devices × mode Where: M, N, and P are clock divider values defined in the control register 4. #Device is the number of the device in cascade. Mode is equal to 1 for continuous data transfer mode and 2 for programming mode. • For slave, SCLK is the input with max allowable speed of 25 MHz (no condition is required) The turbo mode is useful for applications that require more bandwidth for multitasking processing per sampling period. In the turbo mode (see Figure 3–17), the FSs frequency is always the device’s sampling frequency but the SCLK is running at much higher speed than that described in Section 3.6.1. The output SCLK frequency is equal to (MCLK/P) in master mode and up to a maximum speed of 25 MHz for both master and slave AIC14. The data/control frame is still 16-SCLK long and the FS is one-SCLK pulse. Therefore, the DSP can maximize its data processing bandwidth by taking advantage of time available between the end of AIC14s control frame and the next frame-sync FS to process other tasks. |
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