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TLV320AIC12 Datasheet(PDF) 6 Page - Texas Instruments

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Part No. TLV320AIC12
Description  PRODUCT NOTIFICATION
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

TLV320AIC12 Datasheet(HTML) 6 Page - Texas Instruments

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vii
5.7.3
OUTP/OUTM Signal-to-Distortion + Noise When Load
Is 600
5–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.4
DAC Channel Characteristics
5–5
. . . . . . . . . . . . . . . . . . . . . . . .
5.8
BIAS Amplifier Characteristics
5–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
Power-Supply Rejection
5–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10
Power Supply
5–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11
Timing Requirements
5–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12
Layout and Grounding Guidelines for TLV320AIC14
5–13
. . . . . . . . . . . . .
List of Illustrations
Figure
Title
Page
3–1 Microphone Interface
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 INP and INM Internal Self-Biased Circuit
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Single-Ended Input
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 OUTP1/OUTM1 Output
3–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Timing Diagram of FS
3–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Timing Diagram for FSD Output
3–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–7 Cascade Connection (To DSP Interface)
3–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 Master-Slave Frame-Sync Timing in Continuous Data
Transfer Mode
3–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9S2C Programming
3–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–10 I2C Write Sequence
3–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–11 I2C Read Sequence
3–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 Index Register Addresses
3–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 Standard Operation/Programming Mode: Stand-Alone Timing
3–12
. . . . . . . . .
3–14 Standard Operation/Programming Mode: Master-Slave Cascade Timing 3–12
3–15 Standard Operation/Continuous Data Transfer Mode:
Stand-Alone Timing
3–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–16 Standard Operation/Continuous Data Transfer Mode:
Master-Slave Cascade Timing
3–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–17 Timing Diagram for Turbo Operation
3–14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18 Data Frame Format
3–15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–19 Control Frame Data Format
3–15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–20 Broadcast Register Write Example
3–16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Hardware Reset Timing
5–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Serial Communication Timing
5–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 FFT—ADC Channel (–3 dB Input)
5–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 FFT—ADC Channel (–1 dB Input)
5–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 FFT—ADC Channel (–3 dB Input)
5–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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