TAS5121

SLES086A − NOVEMBER 2003 − REVISED MARCH 2004

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6

ELECTRICAL CHARACTERISTICS

PVDD_X = 30.5 V, GVDD_x = 12 V, DVDD connected to DREG via a 100-

Ω resistor, RL = 4 Ω, 8X fs = 384 kHz, TAS5026 PWM processor,

unless otherwise noted

TYPICAL

OVER TEMPERATURE

SYMBOL

PARAMETER

TEST CONDITIONS

TA=25°C

TA=25°C TC=75°C

UNITS

MIN/TYP/

MAX

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

DREG

Voltage regulator

Io = 1 mA

3.3

V

Min

DREG

Voltage regulator

Io = 1 mA

3.3

V

Max

IGVDD_x

Total GVDD supply current, operating

fS = 384 kHz, no load,

50% duty cycle

24

30

mA

Max

IDVDD

DVDD supply current, operating

fS = 384 kHz, no load

1

5

mA

Max

OUTPUT STAGE MOSFETs

RDSon,LS Forward on-resistance, low side

TJ = 25°C

120

132

m

Ω

Max

RDSon,HS Forward on-resistance, high side

TJ = 25°C

120

132

m

Ω

Max

INPUT/OUTPUT PROTECTION

Vuvp,G

Undervoltage protection limit, GVDD

7.6

7

V

Min

Vuvp,G

Undervoltage protection limit, GVDD

7.6

8.2

V

Max

OTW

Overtemperature warning

Static

115

°C

Typ

OTE

Overtemperature error

Static

150

°C

Typ

OC

Overcurrent protection

See Note 1.

9.5

A

Min

STATIC DIGITAL INPUT SPECIFICATION, PWM, PROTECTION MODE SELECTION PINS AND OUTPUT MODE SELECTION PINS

VIH

High-level input voltage

2

V

Min

VIH

High-level input voltage

DVDD

V

Max

VIL

Low-level input voltage

0.8

V

Max

Leakage

Input leakage current

−10

µA

Min

Leakage

Input leakage current

10

µA

Max

OTW/SHUTDOWN (SD)

Internal pullup resistor from OTW and

SD to DVDD

32

22

k

Ω

Min

VOL

Low-level output voltage

IO = 1 mA

0.4

V

Max

(1) To optimize device performance and prevent overcurrent (OC) protection activation, the demodulation filter must be designed with special care.

See Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors

for optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5121.