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NCV887601D1R2G Datasheet(PDF) 11 Page - ON Semiconductor |
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NCV887601D1R2G Datasheet(HTML) 11 Page - ON Semiconductor |
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11 / 15 page  NCV8876 www.onsemi.com 11 The maximum power dissipation in the diode can be calculated as follows: PD + Vf(max) IOUT(max) Where: Pd: Power dissipation in the diode [W] Vf(max): Maximum forward voltage of the diode [V] The 4 amp, 40 V NRVB440MFS SO−8FL package Schottky diode is a recommended device. 10. Design Notes • VOUT serves a dual purpose (feedback and IC power). The VDRV circuit has a current pulse power draw resulting in current flow from the output sense location to the IC. Trace ESL will cause voltage ripple to develop at IC pin VOUT which could affect performance. ♦ Use a 1 mF IC VOUT pin decoupling capacitor close to IC in addition to the VDRV decoupling capacitor. • Classic feedback loop measurements are not possible (VOUT pin serves a dual purpose as a feedback path and IC power). Feedback loop computer modeling recommended. ♦ A step load test for stability verification is recommended. • Compensation ground must be dedicated and connected directly to IC ground. ♦ Do not use vias. Use a dedicated ground trace. • ROSC programming resistor ground must be dedicated and connected directly to IC ground ♦ Do not use vias. Use a dedicated ground trace. • IC ground & current sense resistor ground sense point must be located on the same side of PCB. ♦ Vias introduce sufficient ESR/ESL voltage drop which can degrade the accuracy of the current feedback signal amplitude (signal bounce) and should be avoided. • Star ground should be located at IC ground pad. ♦ This is the location for connecting the compensation and current sense grounds. • The IC architecture has a leading edge ISNS blanking circuit. In some instances, current pulse leading edge current spike RC filter may be required. ♦ If required, 120 pF + 750 W are a recommended evaluation starting point. 11. Determine Feedback Loop Compensation Network The purpose of a compensation network is to stabilize the dynamic response of the converter. By optimizing the compensation network, stable regulation response is achieved for input line and load transients. Compensator design involves the placement of poles and zeros in the closed loop transfer function. Losses from the boost inductor, MOSFET, current sensing and boost diode losses also influence the gain and compensation expressions. The OTA has an ESD protection structure (RESD ≈ 502 W, data not provided in the datasheet) located on the die between the OTA output and the IC package compensation pin (VC). The information from the OTA PWM feedback control signal (VCTRL) may differ from the IC−VC signal if R2 is of similar order of magnitude as RESD. The compensation and gain expressions which follow take influence from the OTA output impedance elements into account . Type−I compensation is not possible due to the presence of RESD. The Figure 13 compensation network corresponds to a Type−II network in series with RESD. The resulting control−output transfer function is an accurate mathematical model of the IC in a boost converter topology. The model does have limitations and a more accurate SPICE model should be considered for a more detailed analysis: • The attenuating effect of large value ceramic capacitors in parallel with output electrolytic capacitor ESR is not considered in the equations . • The efficiency term h should be a reasonable operating condition estimate. Figure 13. NCV8876 OTA and Compensation Rds(on) Vd L Ri COUT VOUT C1 R2 VIN rL rCf C2 ROUT GND ISNS VOUT GDRV VC VCTRL OTA RESD R1 RLOW R0 VREF RGDRV |
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