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SI9145 Datasheet(PDF) 8 Page - Vishay Siliconix |
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SI9145 Datasheet(HTML) 8 Page - Vishay Siliconix |
8 / 10 page Si9145 Vishay Siliconix www.vishay.com 8 Document Number: 70021 S-40710—Rev. K, 19-Apr-04 PIN CONFIGURATIONS 13 VDD VS MODE SELECT OUTPUT DMAX/SS PGND COMP UVLOSET FB NI VREF ENABLE OTS COSC GND ROSC SOIC-16 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 Top View 13 VDD VS MODE SELECT OUTPUT DMAX/SS PGND COMP UVLOSET FB NI VREF ENABLE OTS COSC GND ROSC TSSOP-16 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 Top View ORDERING INFORMATION−SOIC-16 Part Number Temperature Range Si9145BY-T1 25_ to 85_C Si9145BY-T1—E3 −25_ to 85_C ORDERING INFORMATION−TSSOP-16 Part Number Temperature Range Si9145BQ-T1 25_ to 85_C Si9145BQ-T1—E3 −25_ to 85_C PIN DESCRIPTION Pin 1: VDD The positive power supply for all functional blocks except output driver. A bypass capacitor of 0.1 mF (minimum) is recommended. Pin 2: MODE SELECT This pin is used to enable maximum duty cycle limit and set output polarity of controller. When connected to VDD, the maximum duty cycle function is controlled by the DMAX/SSpin. The maximum duty cycle limit is usually used for forward, flyback, and boost converters. The output polarity is high when the PWM circuitry requires the external device to be turned on. When connected to GND, the maximum duty cycle is not limited (usually for buck converters driving a p-channel MOS). The output polarity is low when the PWM circuitry requires the external PMOS to be turned on. Pin 3: DMAX/SS DMAX/SS pin controls the maximum duty cycle achievable by the PWM circuitry when the MODE SELECT = VDD. When DMAX/SS is at less than 1.0 V (typical) the OUTPUT is held low (0% duty cycle). When DMAX/SS is at more than 1.5 V (typical), the PWM circuitry can achieve 100% duty cycle. With voltage at DMAX/SS between 1.0 V and 1.5 V, the maximum duty cycle is proportionally limited to this voltage. The addition of external components can implement a soft start function. Pin 4: COMP This pin is the output of the error amplifier. A compensation network is connected from this pin to the FB pin to stabilize the system. This pin drives one input of the internal pulse width modulation comparator. Pin 5: FB The inverting input of the error amplifier. External resistors are connected to this pin to set the regulated output voltage. The compensation network is also connected to this pin. Pin 6: NI The non-inverting input of the error amplifier. In normal operation it is externally connected to the VREF pin. Pin 7: VREF This pin supplies 1.5 V trimmed to "1.5%. The reference voltage is generated by a band-gap reference. Pin 8: GND Negative return for VDD. |
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