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S93663P2.7T Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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S93663P2.7T Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
3 / 14 page 3 S93662/S93663 2012 2.0 4/18/00 Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the S93662/663 will come out of the high impedance state and, will first output an initial dummy zero bit, then begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start automatic erase and write cycle to the memory location specified in the instruction. The ready/busy status of the S93662/663 can be determined by select- ing the device and polling the DO pin. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start the auto erase cycle of the selected memory location. The ready/busy status of the S93662/663 can be deter- mined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Erase/Write Enable and Disable The S93662/663 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all S93662/663 write and clear instructions, and will prevent any accidental Figure 1. Sychronous Data Timing Figure 2. Read Instruction Timing SK 2012 ILL 3 1.0 DI CS DO t DIS t PD0, t PD1 tCSMIN tCSS tDIS tDIH tSKHI t CSH VALID VALID DATA V ALID t SKLOW SK 2012 ILL4 1.0 CS DI DO tCS STANDBY tHZ HIGH-Z HIGH-Z 11 0 AN AN–1 A0 0 DN DN–1 D1 D0 tPD0 |
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