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SAF7118H Datasheet(PDF) 61 Page - NXP Semiconductors |
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SAF7118H Datasheet(HTML) 61 Page - NXP Semiconductors |
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61 / 173 page  2004 Jul 22 61 Philips Semiconductors Product specification Multistandard video decoder with adaptive comb filter and component video input SAF7118 Table 15 Data types supported by the data slicer block DT[3:0] 62H[3:0] STANDARD TYPE DATA RATE (Mbit/s) FRAMING CODE FC WINDOW HAM CHECK 0000 teletext EuroWST, CCST 6.9375 27H WST625 always 0001 European closed caption 0.500 001 CC625 0010 VPS 5 9951H VPS 0011 wide screen signalling bits 5 1E3C1FH WSS 0100 US teletext (WST) 5.7272 27H WST525 always 0101 US closed caption (line 21) 0.503 001 CC525 0110 (video data selected) 5 none disable 0111 (raw data selected) 5 none disable 1000 teletext 6.9375 programmable general text optional 1001 VITC/EBU time codes (Europe) 1.8125 programmable VITC625 1010 VITC/SMPTE time codes (USA) 1.7898 programmable VITC525 1011 reserved 1100 US NABTS 5.7272 programmable NABTS optional 1101 MOJI (Japanese) 5.7272 programmable (A7H) Japtext 1110 Japanese format switch (L20/22) 5 programmable open 1111 no sliced data transmitted (video data selected) 5 none disable 8.6 Image port output formatter (subaddresses 84H to 87H) The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I port and a decoding and multiplexing unit, which generates the 8 or 16-bit wide output data stream and the accompanied reference and supporting information. The clock for the output interface can be derived from an internal clock, decoder, expansion port, or an externally provided clock which is appropriate for e.g. VGA and frame buffer. The clock can be up to 33 MHz. The scaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84H and 85H: • Output field ID • Start and end of vertical active video range • Start and end of active video line • Data qualifier or gated clock • Actually activated programming page (if CONLH is used) • Threshold controlled FIFO filling flags (empty, full, filled) • Sliced data marker. The discontinuous data stream at the scaler output is accompanied by a data valid flag (or data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the I port data bus (including the HPD pins in 16-bit output mode) are marked with code 00H. The output interface also arbitrates the transfer between scaled video data and sliced text data over the I port output. The bits VITX1 and VITX0 (subaddress 86H) are used to control the arbitration. As a further operation the serialization of the internal 32-bit Dwords to 8-bit or optional 16-bit output, as well as the insertion of the extended ITU 656 codes (SAV/EAV for video data, ANC or SAV/EAV codes for sliced text data) are done here. For handshake with the VGA controller, or other memory or bus interface circuitry, programmable FIFO flags are provided; see Section 8.6.2. |
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