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SAF7118EH Datasheet(PDF) 63 Page - NXP Semiconductors |
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SAF7118EH Datasheet(HTML) 63 Page - NXP Semiconductors |
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63 / 173 page  2004 Jul 22 63 Philips Semiconductors Product specification Multistandard video decoder with adaptive comb filter and component video input SAF7118 8.6.3 TEXT FIFO The data of the internal VBI data slicer is collected in the text FIFO before the transmission over the I port is requested (normally before the video window starts). It is partitioned into two FIFO sections. A complete line is filled into the FIFO before a data transfer is requested. So normally, one line of text data is ready for transfer, while the next text line is collected. Thus sliced text data is delivered as a block of qualified data, without any qualification gaps in the byte stream of the I port. The decoded VBI data is collected in the dedicated VBI data FIFO. After the capture of a line has been completed, the FIFO can be streamed through the image port, preceded by a header, giving line number and standard. The VBI data period can be signalled via the sliced data flag on pin IGP0 or IGP1. The decoded VBI data is lead by the ITU ancillary data header (DID[5:0] 5DH[5:0] at value <3EH) or by SAV/EAV codes selectable by DID[5:0] at value 3EH or 3FH. Pin IGP0 or IGP1 is set if the first byte of the ANC header is valid on the I port bus. It is reset if an SAV occurs. So it may frame multiple lines of text data output, in the event that the video processing starts with a distance of several video lines to the region of text data. Valid sliced data from the text FIFO is available on the I port as long as the IGP0 or IGP1 flag is set and the data qualifier is active on pin IDQ. The decoded VBI data is presented in two different data formats, controlled by bit RECODE. • RECODE = 1: values 00H and FFH will be recoded to even parity values 03H and FCH • RECODE = 0: values 00H and FFH may occur in the data stream as detected. 8.6.4 VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H) Sliced text data and scaled video data are transferred over the same bus, the I port. The mixed transfer is controlled by an arbitration circuit. If the video data is transferred without any interrupt and the video FIFO does not need to buffer any output pixel, the text data is inserted after the end of a scaled video line, normally during the blanking interval of the video. 8.6.5 DATA STREAM CODING AND REFERENCE SIGNAL GENERATION (SUBADDRESSES 84H, 85H AND 93H) As H and V reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data. As an alternative to the gates, H and V trigger pulses are generated on the rising edges of the gates. Due to the dynamic FIFO behaviour of the complete scaler path, the output signal timing has no fixed timing relationship to the real-time input video stream. So fixed propagation delays, in terms of clock cycles, related to the analog input cannot be defined. The data stream is accompanied by a data qualifier. Additionally invalid data cycles are marked with code 00H. If ITU 656 like codes are not required, they can be suppressed in the output stream. As a further option, it is possible to provide the scaler with an external gating signal on pin ITRDY. Thereby making it possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length. The sketched reference signals and events can be mapped to the I port output pins IDQ, IGPH, IGPV, IGP0 and IGP1. For flexible use the polarities of all the outputs can be modified. The default polarity for the qualifier and reference signals is logic 1 (active). Table 19 shows the relevant and supported SAV and EAV coding. |
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