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GXLV Datasheet(PDF) 78 Page - National Semiconductor (TI) |
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GXLV Datasheet(HTML) 78 Page - National Semiconductor (TI) |
78 / 247 page www.national.com 78 Revision 1.1 Processor Programming (Continued) Along with the base address of the page table or the page frame, each DTE or PTE contains attribute bits and a present bit as illustrated in Table 3-28. If the present bit (P) is set in the DTE, the page table is present and the appropriate page table entry is read. If P = 1 in the corresponding PTE (indicating that the page is in memory), the accessed and dirty bits are updated, if necessary, and the operand is fetched. Both accessed bits are set (DTE and PTE), if necessary, to indicate that the table and the page have been used to translate a linear address. The dirty bit (D) is set before the first write is made to a page. The present bits must be set to validate the remaining bits in the DTE and PTE. If either of the present bits are not set, a page fault is generated when the DTE or PTE is accessed. If P = 0, the remaining DTE/PTE bits are avail- able for use by the operating system. For example, the operating system can use these bits to record where on the hard disk the pages are located. A page fault is also generated if the memory reference violates the page pro- tection attributes. Translation Look-Aside Buffer The translation look-aside buffer (TLB) is a cache for the paging mechanism and replaces the two-level page table lookup procedure for TLB hits. The TLB is a four-way set associative 32-entry page table cache that automatically keeps the most commonly used page table entries in the processor. The 32-entry TLB, coupled with a 4 KB page size, results in coverage of 128 KB of memory addresses. The TLB must be flushed when entries in the page tables are changed. The TLB is flushed whenever the CR3 regis- ter is loaded. An individual entry in the TLB can be flushed using the INVLPG instruction. DTE Cache The DTE cache caches the two most recent DTEs so that future TLB misses only require a single page table read to calculate the physical address. The DTE cache is dis- abled following RESET and can be enabled by setting the DTE_EN bit in CCR4[4] (see CCR4 register on page 53). Table 3-28. Directory Table Entry (DTE) and Page Table Entry (PTE) Bit Name Description 31:12 BASE ADDRESS Base Address: Specifies the base address of the page or page table. 11:9 AVAILABLE Available: Undefined and available to the programmer. 8:7 RSVD Reserved: Unavailable to programmer. 6D Dirty Bit: PTE format — If = 1: Indicates that a write access has occurred to the page. DTE format — Reserved. 5A Accessed Flag: If set, indicates that a read access or write access has occurred to the page. 4:3 RSVD Reserved: Set to 0. 2U/S User/Supervisor Attribute: If = 1: Page is accessible by User at privilege level 3. If = 0: Page is accessible by Supervisor only when CPL ≤ 2. 1W/R Write/Read Attribute: If = 1: Page is writable. If = 0: Page is read only. 0P Present Flag: If = 1: The page is present in RAM and the remaining DTE/PTE bits are validated If = 0: The page is not present in RAM and the remaining DTE/PTE bits are available for use by the pro- grammer. |
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