PLL1705

PLL1706

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002

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FUNCTION CONTROL

The built-in functions of the PLL1705 can be controlled in the parallel mode (hardware mode), which uses SR (pin 7), FS1

(pin 5) and FS2 (pin 6). The PLL1706 can be controlled in the serial mode (software mode), which uses a three-wire

interface by ML (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4.

Table 4. Selectable Functions

SELECTABLE FUNCTION

PARALLEL MODE

SERIAL MODE

Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)

Yes

Yes

Sampling rate select (standard/double)

Yes

Yes

Each clock output enable/disable

No

Yes

Power down

No

Yes

PLL1705 (Parallel Mode)

In the parallel mode, the following functions can be selected:

Sampling Frequency Group Select

The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6).

FS2 (PIN 6)

FS1 (PIN 5)

SAMPLING FREQUENCY

LOW

LOW

48 kHz

LOW

HIGH

44.1 kHz

HIGH

LOW

32 kHz

HIGH

HIGH

Reserved

Sampling Rate Select

The sampling rate can be selected by SR (pin 7)

SR (PIN 7)

SAMPLING RATE

LOW

Standard

HIGH

Double

PLL1706 (Serial Mode)

The built-in functions of the PLL1706 are shown in Table 5. These functions are controlled using the ML, MC, and MD serial

control signals.

Table 5. Selectable Functions

SELECTABLE FUNCTION

DEFAULT

Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)

48-kHz group

Sampling rate select (standard/double)

Standard

Each clock output enable/disable

Enabled

Power down

Disabled