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PI6C3991

3.3V High-Speed, Low-Voltage Programmable

7

PS8450B

04/09/01

OperationalModeDescriptions

Figure2.Zero-Skewand/orZero-DelayClockDriver

Figure 2 shows the SuperClock configured as a zero-skew clock

buffer. In this mode the PI6C3991 can be used as the basis for a low-

skew clock distribution tree. When all of the function select inputs

(xF0, xF1) are left open, the outputs are aligned and may each drive

a terminated transmission line to an independent load. The FB input

FB

REF

FS

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

TEST

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

System Clock

REF

LOAD

LOAD

LOAD

LOAD

L1

L2

L3

L4

LENGTH: L1 = L2 = L3 = L4

FB

REF

FS

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

TEST

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

System Clock

REF

LOAD

LOAD

LOAD

LOAD

L1

L2

L3

L4

LENGTH: L1 = L2, L3 < L2 by 6", L4 > L2 by 6"

Figure3.ProgrammableSkewClockDriver

can be tied to any output in this configuration and the operating

frequency range is selected with the FS pin. The low-skew specifi-

cation,coupledwiththeabilitytodriveterminatedtransmissionlines

(with impedances as low as 50 Ohm), allows efficient printed circuit

board design.