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P89C660HBA Datasheet(PDF) 79 Page - NXP Semiconductors |
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P89C660HBA Datasheet(HTML) 79 Page - NXP Semiconductors |
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79 / 89 page  Philips Semiconductors Product data P89C660/P89C662/P89C664/ P89C668 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM 2002 Oct 28 79 AC ELECTRICAL CHARACTERISTICS (12 CLOCK MODE) Tamb = 0 °C to +70 °C, VCC = 5 V ± 10%, or –40 °C to +85 °C, VCC = 5 V ±5%, VSS = 0V1, 2, 3 VARIABLE CLOCK4 33 MHz CLOCK4 SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 57 Oscillator frequency 0 33 – – MHz tLHLL 57 ALE pulse width 2tCLCL–40 – 21 – ns tAVLL 57 Address valid to ALE low tCLCL–25 – 5 – ns tLLAX 57 Address hold after ALE low tCLCL–25 – 5 – ns tLLIV 57 ALE low to valid instruction in – 4tCLCL–65 – 55 ns tLLPL 57 ALE low to PSEN low tCLCL–25 – 5 – ns tPLPH 57 PSEN pulse width 3tCLCL–45 – 45 – ns tPLIV 57 PSEN low to valid instruction in – 3tCLCL–60 – 30 ns tPXIX 57 Input instruction hold after PSEN 0 – 0 – ns tPXIZ 57 Input instruction float after PSEN – tCLCL–25 – 5 ns tAVIV 57 Address to valid instruction in – 5tCLCL–80 – 70 ns tPLAZ 57 PSEN low to address float – 10 – 10 ns Data Memory tRLRH 58, 59 RD pulse width 6tCLCL–100 – 82 – ns tWLWH 58, 59 WR pulse width 6tCLCL–100 – 82 – ns tRLDV 58, 59 RD low to valid data in – 5tCLCL–90 – 60 ns tRHDX 58, 59 Data hold after RD 0 – 0 – ns tRHDZ 58, 59 Data float after RD – 2tCLCL–28 – 32 ns tLLDV 58, 59 ALE low to valid data in – 8tCLCL–150 – 90 ns tAVDV 58, 59 Address to valid data in – 9tCLCL–165 – 105 ns tLLWL 58, 59 ALE low to RD or WR low 3tCLCL–50 3tCLCL+50 40 140 ns tAVWL 58, 59 Address valid to WR low or RD low 4tCLCL–75 – 45 – ns tQVWX 58, 59 Data valid to WR transition tCLCL–30 – 0 – ns tWHQX 58, 59 Data hold after WR tCLCL–25 – 5 – ns tQVWH 59 Data valid to WR high 7tCLCL–130 – 80 – ns tRLAZ 58, 59 RD low to address float – 0 – 0 ns tWHLH 58, 59 RD or WR high to ALE high tCLCL–25 tCLCL+25 5 55 ns External Clock tCHCX 61 High time 17 tCLCL–tCLCX – – ns tCLCX 61 Low time 17 tCLCL–tCHCX – – ns tCLCH 61 Rise time – 5 – – ns tCHCL 61 Fall time – 5 – – ns Shift Register tXLXL 60 Serial port clock cycle time 12tCLCL – 360 – ns tQVXH 60 Output data setup to clock rising edge 10tCLCL–133 – 167 – ns tXHQX 60 Output data hold after clock rising edge 2tCLCL–80 – 50 – ns tXHDX 60 Input data hold after clock rising edge 0 – 0 – ns tXHDV 60 Clock rising edge to input data valid – 10tCLCL–133 – 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz. |
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