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P89C662 Datasheet(PDF) 48 Page - NXP Semiconductors |
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P89C662 Datasheet(HTML) 48 Page - NXP Semiconductors |
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48 / 89 page  Philips Semiconductors Product data P89C660/P89C662/P89C664/ P89C668 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM 2002 Oct 28 48 S0CON Address = 98H Reset Value = 0000 0000B SM0/FE SM1 SM2 REN TB8 RB8 Tl Rl Bit Addressable (SMOD0 = 0/1)* Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) SM1 Serial Port Mode Bit 1 SM0 SM1 Mode Description Baud Rate** 0 0 0 shift register fOSC/6 (6 clock mode) or fOSC/12 (12 clock mode) 0 1 1 8-bit UART variable 1 0 2 9-bit UART fOSC/32 or fOSC/16 (6 clock mode) or fOSC/64 or fOSC/32 (12 clock mode) 1 1 3 9-bit UART variable SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. NOTE: *SMOD0 is located at PCON6. **fOSC = oscillator frequency SU01451 Bit: 7654 321 0 Figure 32. S0CON: Serial Port Control Register |
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