NJ88C22

Characteristic

Units

Conditions

Min.

Typ.

Max.

200

mV RMS 10MHz AC-coupled sinewave

20

MHz

25

°C.

Propagation delay, clock to modulus control MC

30

50

ns

See note 2

Programming Inputs

0·5

µs

0·5

µs

0·2

µs

0·2

µs

0·2

µs

0·2

µs

Clock rise and fall times

0·2

µs

High level threshold

V

See note 1

Low level threshold

0·8

V

See note 1

Hysteresis

1·0

V

See note 1

Phase Detector

Digital phase detector propagation delay

500

ns

Gain programming resistor, RB

5

k

Ω

Hold capacitor, CH

1

nF

See note 3

Programming capacitor, CAP

1

nF

Output resistance, PDA

5

k

Ω

Characteristic

Units

Conditions

Min.

Typ.

Max.

Supply current

5·5

mA

1.5

mA

Modulus Control Output (MC)

High level

4·6

V

Low level

0·4

V

Lock Detect Output (LD)

Low level

0·4

V

Open drain pull-up voltage

7·0

V

PDB Output

High level

4·6

V

Low level

0·4

V

3-state leakage current

±0·1

µA

2

Test conditions unless otherwise stated:

DC Characteristics

Value

AC Characteristics

All timing periods

are referenced to

the negative

transition of the

clock waveform

Value

0 to 5V

square

wave

NOTES

1. Data, Clock and Enable inputs are high impedance Schmitt buffers without pull-up resistors; they are therefore not TTL compatible.

2. All counters have outputs directly synchronous with their respective clock rising edges.

3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant

to the loop. An external 1nF hold capacitor will give a maximum time constant of 5

µs.

4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the signal/osc.

frequency inputs.