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GS81302T06 Datasheet(PDF) 7 Page - GSI Technology |
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GS81302T06 Datasheet(HTML) 7 Page - GSI Technology |
7 / 29 page Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.03c 11/2011 7/29 © 2011, GSI Technology GS81302T06/11/20/38E-500/450/400/350 Background Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications. Therefore, the SigmaDDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half. Burst Operations Read and write operations are "Burst" operations. In every case where a read or write command is accepted by the SRAM, it will respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in the timing diagrams. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted. Deselect Cycles Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer and then execute the deselect command, returning the output drivers to High-Z. A high on the LD pin prevents the RAM from loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations. SigmaDDR-II+ Burst of 2 SRAM Read Cycles The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read command (LD low and R/W high) is clocked into the SRAM by a rising edge of K. SigmaDDR-II+ Burst of 2 SRAM Write Cycles The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command (LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures data in on the next rising edge of K, for a total of two transfers per address load. Special Functions Byte Write and Nybble Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2-beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NWx” may be substituted in all the discussion above. Resulting Write Operation Byte 1 D0–D8 Byte 2 D9–D17 Byte 3 D0–D8 Byte 4 D9–D17 Written Unchanged Unchanged Written Beat 1 Beat 2 |
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