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GS8182T08 Datasheet(PDF) 11 Page - GSI Technology |
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GS8182T08 Datasheet(HTML) 11 Page - GSI Technology |
11 / 36 page GS8182T08/09/18/36BD-400/375/333/300/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.04c 11/2011 11/36 © 2007, GSI Technology FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaDDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 175 Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and tempera- ture. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. Common I/O SigmaDDR-II B2 SRAM Truth Table Kn LD R/W DQ Operation A + 0 A + 1 ↑ 1 X Hi-Z Hi-Z Deselect ↑ 0 0 D@Kn+1 D@Kn+1 Write ↑ 0 1 Q@Kn+1 or Cn+1 Q@Kn+2 or Cn+2 Read Note: Q is controlled by K clocks if C clocks are not used. B2 Byte Write Clock Truth Table BW BW Current Operation D D K ↑ (tn+1) K ↑ (tn+2) K ↑ (tn) K ↑ (tn+1) K ↑ (tn+2) T T Write Dx stored if BWn = 0 in both data transfers D1 D2 T F Write Dx stored if BWn = 0 in 1st data transfer only D1 X F T Write Dx stored if BWn = 0 in 2nd data transfer only X D2 F F Write Abort No Dx stored in either data transfer X X Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more BWn = 0, then BW = “T”, else BW = “F”. |
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