GS8182S08/09/18/36BD-400/375/333/300/250/200/167

18Mb Burst of 2

400 MHz–167 MHz

1.8 V and 1.5 V I/O

165-Bump BGA

Commercial Temp

Industrial Temp

Rev: 1.03c 11/2011

1/36

© 2007, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Features

• Simultaneous Read and Write SigmaSIO™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• DLL circuitry for wide output data valid window and future

frequency scaling

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 36Mb, and 72Mb and

future 144Mb devices

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaSIO DDR-II™ Family Overview

GS8182S08/09/18/36BD are built in compliance with the

SigmaSIO DDR-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 18,874,368-bit (18Mb)

SRAMs. These are the first in a family of wide, very low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

165-Bump, 13 mm x 15 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

Bottom View

JEDEC Std. MO-216, Variation CAB-1

Clocking and Addressing Schemes

A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous

device. It employs dual input register clock inputs, K and K.

The device also allows the user to manipulate the output

register clock input quasi independently with dual output

register clock inputs, C and C. If the C clocks are tied high, the

K clocks are routed internally to fire the output registers

instead. Each Burst of 2 SigmaSIO DDR-II SRAM also

supplies Echo Clock outputs, CQ and CQ, which are

synchronized with read data output. When used in a source

synchronous clocking scheme, the Echo Clock outputs can be

used to fire input registers at the data’s destination.

Each internal read and write operation in a SigmaSIO DDR-II

B2 RAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaSIO DDR-II B2 is always one address pin less

than the advertised index depth (e.g., the 2M x 8 has a 1M

addressable index).

Parameter Synopsis

-400

-375

-333

-300

-250

-200

-167

tKHKH

2.5 ns

2.67 ns

3.0 ns

3.3 ns

4.0 ns

5.0 ns

6.0 ns

tKHQV

0.45 ns

0.45 ns

0.45 ns

0.45 ns

0.45 ns

0.45 ns

0.5 ns