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LTC4257IDD-1 Datasheet(PDF) 11 Page - Linear Technology |
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LTC4257IDD-1 Datasheet(HTML) 11 Page - Linear Technology |
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11 / 20 page  LTC4257-1 11 42571fa accomplished by a dual level current limit. At turn on before C1 is charged, the LTC4257-1 current limit is set to the low level. After C1 is charged up and the VOUT – VIN voltage difference is below the power good threshold, the LTC4257-1 switches to the high level current limit. The dual level current limit allows legacy PSEs with limited current sourcing capability to power up the PD while also allowing the PD to draw full power from an IEEE 802.3af PSE. The dual level current limit also allows use of arbitrarily large load capacitors. The IEEE 802.3af specification man- dates that at turn on the PD not exceed the inrush current limit for more than 50ms. The LTC4257-1 is not restricted by the 50ms time limit because the load capacitor is charged with a current below the IEEE inrush current limit specification. Therefore, it is possible to use larger load capacitors with the LTC4257-1. As the LTC4257-1 switches from the low to the high level current limit, a momenatry increase in current can be observed. This current spike is a result of the LTC4257-1 charging the last 1.5V at the high level current limit. When charging a 10 µF capacitor, the current spike is typically 100 µs wide and 125% of the nominal low level current limit. The LTC4257-1 stays in the high level current limit mode until the input voltage drops below the UVLO turn-off threshold. This dual level current limit provides the sys- tem designer with the flexibility to design PDs which are compatible with legacy PSEs while also being able to take advantage of the higher power allocation available in an IEEE 802.3af system. During the current limited turn on, a large amount of power is dissipated in the power MOSFET. The LTC4257-1 is designed to accept this thermal load and is thermally protected to avoid damage to the onboard power MOSFET. Note that in order to adhere to the IEEE 802.3af standard, it is necessary for the PD designer to ensure the PD steady- state power consumption falls within the limits shown in Table 2. Power Good The LTC4257-1 includes a power good circuit (Figure 7) that is used to indicate to the PD circuitry that load capacitor C1 is fully charged and that the PD can start DC/DC converter operation. The power good circuit moni- tors the voltage across the internal power MOSFET and PWRGD is asserted when the voltage drops below 1.5V. The power good circuit includes a large amount of hyster- esis to allow the LTC4257-1 to operate near the current limit point without inadvertently disabling PWRGD. The MOSFET voltage must increase to 3V before PWRGD is disabled. APPLICATIO S I FOR ATIO Figure 7. LTC4257-1 Power Good PWRGD C1 5 µF MIN VIN 6 4 VOUT 1.125V 300k 300k R9 100k 5 LTC4257-1 THERMAL SHUTDOWN UVLO 42571 F07 TO PSE PD LOAD SHDN + – + + – |
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