LT3460

4

3460f

PI FU CTIO S

BLOCK DIAGRA

SW (Pin 1/Pin 1): Switch Pin. Connect inductor/diode

here. Minimize trace at this pin to reduce EMI.

GND (Pin 2/Pins 2 and 5): Ground Pin. Tie directly to local

ground plane.

FB (Pin 3/Pin 3): Feedback Pin. Reference

voltage is 1.255V. Connect resistor divider tap here.

SHDN (Pin 4/Pin 4): Shutdown Pin. Tie to 1.5V or higher

to enable device; 0.4V or less to disable device. Also

functions as soft-start. Use RC filter (47k, 47nF typ) as

shown in Figure 1.

bypassed.

OPERATIO

The LT3460 uses a constant frequency, current mode

control scheme to provide excellent line and load regula-

tion. Operation can be best understood by referring to the

block diagram in Figure 1. At the start of each oscillator

cycle, the SR latch is set, which turns on the power switch

Q1. A voltage proportional to the switch current is added

to a stabilizing ramp and the resulting sum is fed into the

positive terminal of the PWM comparator A2. When this

voltage exceeds the level at the negative input of A2, the SR

latch is reset turning off the power switch. The level at the

negative input of A2 is set by the error amplifier A1, and is

simply an amplified version of the difference between the

feedback voltage and the reference voltage of 1.255V. In

this manner, the error amplifier sets the correct peak

current level to keep the output in regulation. If the error

amplifier’s output increases, more current is delivered to

the output; if it decreases, less current is delivered.

–

+

–

+

–

+

5

1

3

2

∑

R1 (EXTERNAL)

R2 (EXTERNAL)

FB

SHUTDOWN

SHDN

RAMP

GENERATOR

1.255V

REFERENCE

1.3MHz

OSCILLATOR

R

S

Q

4

A1

A2

COMPARATOR

DRIVER

SW

Q1

0.1

Ω

GND

(PINS 2 AND 5 SC70 PACKAGE)

(PIN 6 SC70 PACKAGE)

FB

3460 BD

Figure 1. Block Diagram

(ThinSOT/SC70 Packages)