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LNBH21 Datasheet(PDF) 6 Page - STMicroelectronics

Part No. LNBH21
Description  LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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LNBH21 Datasheet(HTML) 6 Page - STMicroelectronics

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However, there could be some cases in which an highly capacitive load on the output may cause a difficult
start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in
static mode (PCL=HIGH) and then switching to the dynamic mode (PCL=LOW) after a chosen amount of
time. When in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns
LOW when the overload condition is cleared.
This IC is also protected against overheating: when the junction temperature exceeds 150°C (typ.), the
step-up converter and the linear regulator are shut off, and the OTF SR bit is set to HIGH. Normal
operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 140°C (typ.).
(*): External components are needed to comply to bi-directional DiSEqCTM bus hardware requirements. Full compliance of the whole appli-
cation with DiSEqCTM specifications is not implied by the use of this IC
I2C BUS INTERFACE
Data transmission from main µP to the LNBH21 and viceversa takes place through the 2 wires I2C bus
interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be
externally connected).
DATA VALIDITY
As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
START AND STOP CONDITIONS
As shown in fig.2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must
be sent before each START condition.
BYTE FORMAT
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
ACKNOWLEDGE
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
3). The peripheral (LNBH21) that acknowledges has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which
has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA
line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH21 won't generate the
acknowledge if the VCC supply is below the Undervoltage Lockout threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the LNBH21, the µP can use a simpler transmission: simply it waits
one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking and decreases the noise immunity.
Figure 1 : DATA VALIDITY ON THE I2CBUS


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