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LNBH21 Datasheet(PDF) 8 Page - STMicroelectronics |
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LNBH21 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 20 page LNBH21 8/20 TRANSMITTED DATA (I2C BUS WRITE MODE) When the R/W bit in the chip address is set to 0, the main µP can write on the System Register (SR) of the LNBH21 via I2C bus. Only 6 bits out of the 8 available can be written by the µP, since the remaining 2 are left to the diagnostic flags, and are read-only. X= don't care. Values are typical unless otherwise specified RECEIVED DATA (I2C bus READ MODE) The LNBH21 can provide to the Master a copy of the SYSTEM REGISTER information via I2C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following master generated clocks bits, the LNBH21 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: - acknowledge the reception, starting in this way the transmission of another byte from the LNBH21; - no acknowledge, stopping the read mode communication. While the whole register is read back by the µP, only the two read-only bits OLF and OTF convey diagnostic informations about the LNBH21. Values are typical unless otherwise specified. Values are typical unless otherwise specified POWER-ON I2C INTERFACE RESET The I2C interface built in the LNBH21 is automatically reset at power-on. As long as the VCC stays below the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I2C command and the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the VCC rises above 7.3V typ, the I 2C interface becomes operative and the SR can be configured by the main µP. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the Power-On reset circuit. ADDRESS PIN Connecting this pin to GND the Chip I2C interface address is 0001000, but, it is possible to choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 10). PCL TTX TEN LLC VSEL EN OTF OLF Function 001 X X VO =13.25 V, VUP = 15.25 V 011 X X VO =18V,VUP=20 V 101 X X VO =14.25 V, VUP = 16.25 V 111 X X VO =19.5V,VUP =21.5V 0 1 X X 22KHz is controlled by DSQIN pin 1 1 X X 22KHz tone is ON, DSQIN pin disabled 01 X X VORX output is ON, output voltage controlled by VSEL and LLC 1X 1X X VOTX output is ON, 22KHz controlled by DSQIN or TEN, output voltage level controlled by VSEL and LLC 0 1 X X Pulsed (dynamic) current limiting is selected 1 1 X X Static current limiting is selected X XXXX 0 X X Power blocks disabled PCL TTX TEN LLC VSEL EN OTF OLF Function These bits are read exactly the same as they were left after last write operation 0 TJ<140°C, normal operation 1 TJ>150°C, power block disabled 0 IOUT<IOMAX, normal operation 1 IOUT>IOMAX, overload protection triggered |
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Similar Description - LNBH21 |
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