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NCP1081 Datasheet(PDF) 13 Page - ON Semiconductor

Part No. NCP1081
Description  Integrated High Power PoE-PD Interface & DC-DC Converter Contr
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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NCP1081 Datasheet(HTML) 13 Page - ON Semiconductor

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NCP1081
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13
As soon as the application is powered by the DC-DC
converter and completes initialization, the microprocessor
should check if the NCP1081 detected a two event hardware
classification by reading its digital input (pin IN1 in this
example). If pin IN1 is low, the application knows power is
supplied by a IEEE802.3at compliant PSE, and can deliver
power up to the level specified by the IEEE802.3at standard.
Otherwise the application will have to perform a Layer 2
classification with the PSE. There are several scenarios for
which the NCP1081 will not enable its nCLASS_AT pin:
The PSE skipped the classification phase.
The PSE performed a one event hardware classification
(it can be a IEEE802.3af or a 802.3at compliant PSE
with Layer 2 engine).
The PSE performed a two event hardware classification
but it did not properly control the input voltage in the
mark voltage window, (for example it crossed the reset
range).
Power Mode
When the classification hand−shake is completed, the
PSE and PD devices move into the operating mode.
Under Voltage Lock Out (UVLO)
The NCP1081 incorporates an under voltage lock out
(UVLO) circuit which monitors the input voltage and
determines when to apply power to the DC−DC controller.
To use the default settings for UVLO (see Table 3), the pin
UVLO must be connected to VPORTN1,2. In this case the
signature resistor has to be placed directly between
VPORTP and VPORTN1,2, as shown in Figure 9.
Figure 9. Default UVLO Settings
UVLO
VPORTP
VPORTN1,2
NCP1081
VPORT
Rdet
To define the UVLO threshold externally, the UVLO pin
must be connected to the center of an external resistor
divider between VPORTP and VPORTN1,2 as shown in
Figure 10. The series resistance value of the external
resistors must add to 25.5 k
W and replaces the internal
signature resistor.
Figure 10. External UVLO Configuration
UVLO
VPORTN1,2
NCP1081
VPORT
R2
R1
VPORTP
For a Vuvlo_on desired turn−on voltage threshold, R1 and
R2 can be calculated using the following equations:
R1 ) R2 + Rdet
R2 + 1.2
Vulvo_on
Rdet
When using the external resistor divider, the NCP1081 has
an external reference voltage hysteresis of 15 percent typical.
Inrush and Operational Current Limitations
The inrush current limit and the operational current limit
are programmed individually by an external Rinrush and
Rilim1 resistors respectively connected between INRUSH
and VPORTN1,2, and between ILIM1 and VPORTN1,2 as
shown in Figure 11.


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