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NCP1081 Datasheet(PDF) 12 Page - ON Semiconductor |
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NCP1081 Datasheet(HTML) 12 Page - ON Semiconductor |
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NCP1081 http://onsemi.com 12 Figure 7. Hardware Physical Classification Event Sequence 1st Class Event Class range Mark Range Reset Range 2 Fingers Classification with 0 V 5.4 V 9.5 V 13 V 20.5 V UVLO_on Power On Detection PSE identified as type 2 PSE (at) PSE Type identification: Number of Mark Event: 0 1 2 X Operation Mode: Mark Events (.at spec) 1st Mark Event 2nd Class Event 2nd Mark Event PSE identified by default as type 1 PSE (af) nCLASS_AT Indicator The nCLASS_AT active low open drain output pin can be used to notify to the microprocessor of the powered device that the PSE performed a one or two event hardware classification. If a two event hardware classification has occured and once the PD application is supplied power by the NCP1081 DC-DC converter, the nCLASS_AT pin will be pulled down to ARTN by the internal low voltage NMOS switch (ARTN is the ground connection of the DC-DC converter). Otherwise, nCLASS_AT will be disabled and will be pulled up to VDDL (3.3 V typ) via an internal current source (20 mA typ) and via the external pull-up resistor. The following scheme illustrates how the nCLASS_AT pin may be configured with the processor of the powered device. An opto-coupler is used to guarantee full isolation between the Ethernet cable and the application. Figure 8. Isolated nClass_AT Communication with the Powered Device Application ARTN NCP1081 nCLASS_AT Class_AT VDDL VDDL Csup Powered Device Application Rled Opto 1 Rbip Isolation VSUP Microprocessor Microcontroller IN1 IN2 GND Layer 2 Engine Features (Isolated DC/DC converter) or 20 mA |
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