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K6F3216T6M Datasheet(PDF) 5 Page - Samsung semiconductor

Part No. K6F3216T6M
Description  2M x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K6F3216T6M Datasheet(HTML) 5 Page - Samsung semiconductor

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K6F3216T6M Family
Revision 1.0
November 2002
5
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
CL1)
1. Including scope and jig capacitance
R22)
R12)
VTM3)
2. R1=3070
, R2=3150Ω
3. VTM =2.8V
DATA RETENTION CHARACTERISTICS
1. 1) CS1
≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or
2) 0
≤CS2≤0.2V(CS2 controlled)
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
VDR
CS1
≥Vcc-0.2V1), VIN≥0V
1.5
-
3.6
V
Data retention current
IDR
Vcc=1.5V, CS1
≥Vcc-0.2V1), VIN≥0V
-
-
20
µA
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
AC CHARACTERISTICS ( Vcc=2.7~3.3V, Industrial product:TA=-40 to 85
°C )
Parameter List
Symbol
Speed
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
tRC
55
-
70
-
ns
Address access time
tAA
-
55
-
70
ns
Chip select to output
tCO1, tCO2
-
55
-
70
ns
Output enable to valid output
tOE
-
25
-
35
ns
UB, LB valid to data output
tBA
-
55
-
70
ns
Chip select to low-Z output
tLZ1, tLZ2
10
-
10
-
ns
UB, LB enable to low-Z output
tBLZ
10
-
10
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
ns
Chip disable to high-Z output
tHZ1, tHZ2
0
20
0
25
ns
UB, LB disable to high-Z output
tBHZ
0
20
0
25
ns
Output disable to high-Z output
tOHZ
0
20
0
25
ns
Output hold from address change
tOH
10
-
10
-
ns
Write
Write cycle time
tWC
55
-
70
-
ns
Chip select to end of write
tCW1, tCW2
45
-
60
-
ns
Address set-up time
tAS
0
-
0
-
ns
Address valid to end of write
tAW
45
-
60
-
ns
UB, LB Valid to End of Write
tBW
45
-
60
-
ns
Write pulse width
tWP
40
-
50
-
ns
Write recovery time
tWR
0
-
0
-
ns
Write to output high-Z
tWHZ
0
20
0
20
ns
Data to write time overlap
tDW
25
-
30
-
ns
Data hold from write time
tDH
0
-
0
-
ns
End write to output low-Z
tOW
5
-
5
-
ns


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