IDT72V255LA15PFI datasheet(11/27 Pages) IDT

Part #	IDT72V255LA15PFI

Description	3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™

8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

If FWFT mode is selected, the FIFO will mark the beginning of the

Retransmit setup by setting

OR HIGH. During this period, the internal read

pointer is set to the first location of the RAM array.

When

OR goes LOW, Retransmit setup is complete; at the same time, the

contents of the first location appear on the outputs. Since FWFT mode is

selected, the first word appears on the outputs, no LOW on

REN is

necessary. Reading all subsequent words requires a LOW on

REN to

enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT

Mode), for the relevant timing diagram.

For either IDT Standard mode or FWFT mode, updating of the

PAE, HF

and

PAF flags begin with the rising edge of RCLK that RT is setup. PAE is

synchronized to RCLK, thus on the second rising edge of RCLK after

RT is

setup, the

PAE flag will be updated. HF is asynchronous, thus the rising

edge of RCLK that

RT is setup will update HF. PAF is synchronized to

WCLK, thus the second rising edge of WCLK that occurs tSKEW after the

rising edge of RCLK that

RT is setup will update PAF. RT is synchronized to

RCLK.

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