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IDT72V8980 Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT72V8980 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 11 page  1 AUGUST 2003 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256 IDT72V8980 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5705/5 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp. FUNCTIONAL BLOCK DIAGRAM Microprocessor Interface Control Register Timing Unit RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 ODE F0i C4i VCC CS DS R/ W A0 A5/ GND CCO DTA D0/ D5 5705 drw01 Receive Serial Data Streams Data Memory Output MUX Connection Memory RESET(1) Transmit Serial Data Streams FEATURES: ••••• 256 x 256 channel non-blocking switch ••••• Serial Telecom Bus Compatible (ST-BUS®) ••••• 8 RX inputs—32 channels at 64 Kbit/s per serial line ••••• 8 TX output—32 channels at 64 Kbit/s per serial line ••••• Three-state serial outputs ••••• Microprocessor Interface (8-bit data bus) ••••• 3.3V Power Supply ••••• Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 48-pin Small Shrink Outline Package (SSOP), and 44-pin Plastic Quad Flatpack (PQFP) ••••• Operating Temperature Range -40 °°°°°C to +85°°°°°C ••••• 3.3V I/O with 5V Tolerant Inputs DESCRIPTION: The IDT72V8980 is a ST-BUS® compatible digital switch controlled by a microprocessor. The IDT72V8980 can handle as many as 256, 64 Kbit/s input and output channels. Those 256 channels are divided into 8 serial inputs and outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form a multiplexed 2.048 Mb/s stream. FUNCTIONAL DESCRIPTION A functional block diagram of the IDT72V8980 device is shown on below. The serial ST-BUS® streams operate continuously at 2.048 Mb/s and are arrangedin125 µswideframeseachcontaining32,8-bitchannels. Eightinput (RX0-7) and eight output (TX0-7) serial streams are provided in the IDT72V8980 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock ( C4i)forthedevice is 4.096 MHz. The received serial data is internally converted to a parallel format by the on chip serial-to-parallel converters and stored sequentially in a 256-position DataMemory.Byusinganinternalcounterthatisresetbytheinput8KHzframe pulse, F0i, the incoming serial data streams can be framed and sequentially addressed. NOTE: 1. The RESET Input is only provided on the SSOP package. |
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