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IDT72V8980 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT72V8980
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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6
Commercial Temperature Range
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
TABLE 4 — CONNECTION MEMORY HIGH REGISTER
TABLE 5 — CONNECTION MEMORY LOW REGISTER
TABLE 3 — CONTROL REGISTER CONFIGURATION
Bit
Name
Description
7
SM (Split Memory)
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except
when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the
operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.
6
PE (Processor Mode)
When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE
pin is LOW. When 0, the Connection Memory bits for each channel determine what is output.
5
unused
4-3
MS1-MS0
0-0 - Not to be used.
(Memory Select Bits)
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
2-0
STA2-0
The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the
(Stream Address Bits)
subsection of memory made accessible for subsequent operations.
76543210
Mode Control
Memory Select
Bits
(unused)
Bits
Stream Address Bits
Bit
Name
Description
2
CS (Channel Source)
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determine the source of the connection to the location's channel and stream.
1
CCO (CCO Bit)
This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first.
0
OE (Output Enable)
If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output drive for the location's
channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing
switching matrices to be constructed. A 1 enables the driver and a 0 disables it.
76543210
No Corresponding Memory
- These bits give 0s if read
Per Channel Control Bits
Bit
Name
Description
7-5(1)
Stream Address Bits*
The number expressed in binary notation on these 3 bits are the number of the stream for the source of the connection.
Bit 7 is the most significant bit, e.g., If bit 7 is 1, bit 6 is 0 and bit 5 is 0 then the source of the connection is a channel on
RX4.
4-0(1)
Channel Address Bits*
The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the
connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4
is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
76543210
Stream Address Bits
Channel Address Bits
NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with
this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.




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